• 1159 Citations
  • 15 h-Index
1989 …2020

Research output per year

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Research Output

2020

Efficient systolic-array redundancy architecture for offline/online repair

Cho, K., Lee, I., Lim, H. & Kang, S., 2020 Feb, In : Electronics (Switzerland). 9, 2, 338.

Research output: Contribution to journalArticle

Open Access

GPU-Based Redundancy Analysis Using Concurrent Evaluation

Kim, T. H., Lee, H. & Kang, S., 2020 Mar, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28, 3, p. 805-817 13 p., 8935214.

Research output: Contribution to journalArticle

2019

2-D Failure Bitmap Compression Using Line Fault Marking Method

Cho, K., Lee, Y. W., Seo, S. & Kang, S., 2019 Feb 22, Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc., p. 21-22 2 p. 8649886. (Proceedings - International SoC Design Conference 2018, ISOCC 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3D Memory Formed of Unrepairable Memory Dice and Spare Layer

Han, D., Lee, H., Lee, S., Moon, M. & Kang, S., 2019 Feb 22, Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference. Institute of Electrical and Electronics Engineers Inc., p. 1362-1366 5 p. 8650278. (IEEE Region 10 Annual International Conference, Proceedings/TENCON; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A low-cost concurrent TSV test architecture with lossless test output compression scheme

Lee, Y. W., Lim, H., Seo, S., Cho, K. & Kang, S., 2019 Aug 1, In : PloS one. 14, 8, e0221043.

Research output: Contribution to journalArticle

Open Access

An efficient BIRA utilizing characteristics of spare pivot faults

Cho, K., Lee, Y. W., Seo, S. & Kang, S., 2019 Mar, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38, 3, p. 551-561 11 p., 8323241.

Research output: Contribution to journalArticle

1 Citation (Scopus)

An Efficient Scan Chain Diagnosis for Stuck-at and Transition Faults

Lim, H., Jang, S., Kim, S. & Kang, S., 2019 Oct, Proceedings - 2019 International SoC Design Conference, ISOCC 2019. Institute of Electrical and Electronics Engineers Inc., p. 295-296 2 p. 9078517. (Proceedings - 2019 International SoC Design Conference, ISOCC 2019; vol. 2019-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A Software-based Scan Chain Diagnosis for Double Faults in A Scan Chain

Lim, H., Jang, S. & Kang, S., 2019 Feb 22, Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc., p. 265-266 2 p. 8649930. (Proceedings - International SoC Design Conference 2018, ISOCC 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A Test Methodology for Neural Computing Unit

Cheong, M., Lee, I. & Kang, S., 2019 Feb 22, Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc., p. 11-12 2 p. 8649896. (Proceedings - International SoC Design Conference 2018, ISOCC 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dynamic built-in redundancy analysis for memory repair

Lee, H., Han, D., Lee, S. & Kang, S., 2019 Oct, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27, 10, p. 2365-2374 10 p., 8746162.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test

Oh, H., Kim, H., Lee, S. & Kang, S., 2019 Feb 22, Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc., p. 7-8 2 p. 8649911. (Proceedings - International SoC Design Conference 2018, ISOCC 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Highly reliable redundant TSV architecture for clustered faults

Lee, I., Cheong, M. & Kang, S., 2019 Mar, In : IEEE Transactions on Reliability. 68, 1, p. 237-247 11 p., 8444082.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Low Power Scan Chain Architecture Based on Circuit Topology

Kim, H., Oh, H., Lee, S. & Kang, S., 2019 Feb 22, Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc., p. 267-268 2 p. 8649956. (Proceedings - International SoC Design Conference 2018, ISOCC 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Neural Network Reliability Enhancement Approach Using Dropout Underutilization in GPU

Lee, D., Lim, H., Kim, T. H. & Kang, S., 2019 Feb 22, Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference. Institute of Electrical and Electronics Engineers Inc., p. 2281-2286 6 p. 8650184. (IEEE Region 10 Annual International Conference, Proceedings/TENCON; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Test-Friendly Data-Selectable Self-Gating (DSSG)

Kim, J., Lee, S. & Kang, S., 2019 Aug, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27, 8, p. 1972-1976 5 p., 8728193.

Research output: Contribution to journalArticle

TSV repair architecture for clustered faults

Jang, J., Cheong, M. & Kang, S., 2019 Jan, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38, 1, p. 190-194 5 p., 8299466.

Research output: Contribution to journalArticle

2018

A debug scheme to improve the error identification in post-silicon validation

Choi, I., Jung, W., Oh, H. & Kang, S., 2018 Sep, In : PloS one. 13, 9, e0202216.

Research output: Contribution to journalArticle

1 Citation (Scopus)

An area-efficient BIRA with 1-D spare segments

Kim, D., Lee, H. & Kang, S., 2018 Jan, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26, 1, p. 206-210 5 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

An efficient built-in self-repair scheme for area reduction

Cho, K., Lee, Y. W., Seo, S. & Kang, S., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 105-106 2 p. (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A new repair scheme for TSV-based 3D memory using base die repair cells

Han, D., Lee, H., Kim, D. & Kang, S., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 11-12 2 p. (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A selective error data capture method using on-chip DRAM for silicon debug of multi-core design

Oh, H., Kim, H., Lim, J. & Kang, S., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 121-122 2 p. (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A Statistic-Based Scan Chain Reordering for Energy-Quality Scalable Scan Test

Seo, S., Cho, K., Lee, Y. W. & Kang, S., 2018 Sep, In : IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 8, 3, p. 391-403 13 p., 8355813.

Research output: Contribution to journalArticle

1 Citation (Scopus)
1 Citation (Scopus)

LARECD: Low area overhead and reliable error correction DMR architecture

Lim, H., Kim, T., Lee, D. & Kang, S., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 27-28 2 p. (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Test data reduction method based on berlekamp-massey algorithm

Lim, H., Kim, J., Kang, S. & Kang, S., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 123-124 2 p. (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Test resource reused debug scheme to reduce the post-silicon debug cost

Choi, I., Oh, H., Lee, Y. W. & Kang, S., 2018 Dec 1, In : IEEE Transactions on Computers. 67, 12, p. 1835-1839 5 p., 8359333.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Thermal aware test scheduling for NTV circuit

Lim, J., Oh, H., Kim, H. & Kang, S., 2018 Apr, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 37, 4, p. 906-910 5 p., 7984890.

Research output: Contribution to journalArticle

1 Citation (Scopus)
2017

A low-cost DAC BIST structure using a resistor loop

Jang, J., Kim, H. & Kang, S., 2017 Feb, In : PloS one. 12, 2, e0172331.

Research output: Contribution to journalArticle

A new online test and debug methodology for automotive camera image processing system

Oh, H., Choi, I. & Kang, S., 2017 Jan 3, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., p. 370-371 2 p. 7803978. (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

An on-chip error detection method to reduce the post-silicon debug time

Oh, H., Han, T., Choi, I. & Kang, S., 2017 Jan 1, In : IEEE Transactions on Computers. 66, 1, p. 38-44 7 p., 7464321.

Research output: Contribution to journalArticle

5 Citations (Scopus)

A novel X-filling method for capture power reduction

Kim, H., Oh, H., Lim, J. & Kang, S., 2017, In : ieice electronics express. 14, 23, 20171093.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Broadcast scan compression based on deterministic pattern generation algorithm

Lim, H., Seo, S., Kang, S. & Kang, S., 2017 May 2, Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017. IEEE Computer Society, p. 449-453 5 p. 7918357. (Proceedings - International Symposium on Quality Electronic Design, ISQED).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation

Jang, J., Cheong, M., Ahn, J. H., Lim, S. K. & Kang, S., 2017 Mar, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 3, p. 1178-1182 5 p., 7747508.

Research output: Contribution to journalArticle

1 Citation (Scopus)

DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores

Oh, H., Choi, I. & Kang, S., 2017 Sep 1, In : IEEE Transactions on Computers. 66, 9, p. 1504-1517 14 p., 7872459.

Research output: Contribution to journalArticle

5 Citations (Scopus)

Dynamic voltage frequency scaling-aware refresh management for 3D DRAM over processor architecture

Lim, J., Kim, H., Oh, H. & Kang, S., 2017 Jul 6, In : Electronics Letters. 53, 14, p. 910-912 3 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

FRESH: A New Test Result Extraction Scheme for Fast TSV Tests

Park, J., Lim, H. & Kang, S., 2017 Feb, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36, 2, p. 336-345 10 p., 7488276.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs

Lee, Y. W., Lim, H. & Kang, S., 2017 Oct, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36, 10, p. 1759-1763 5 p., 7572121.

Research output: Contribution to journalArticle

4 Citations (Scopus)

Hardware-Efficient Built-In Redundancy Analysis for Memory with Various Spares

Kim, J., Lee, W., Cho, K. & Kang, S., 2017 Mar, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 3, p. 844-856 13 p., 7572978.

Research output: Contribution to journalArticle

10 Citations (Scopus)

Low cost endurance test-pattern generation for multi-level cell flash memory

Cha, J., Cho, K., Yu, S. & Kang, S., 2017 Feb, In : Journal of Semiconductor Technology and Science. 17, 1, p. 147-155 9 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder

Seo, S., Lim, H., Kang, S. & Kang, S., 2017 May 2, Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017. IEEE Computer Society, p. 191-195 5 p. 7918315. (Proceedings - International Symposium on Quality Electronic Design, ISQED).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Proof of concept of home IoT connected vehicles

Kim, Y., Oh, H. & Kang, S., 2017 Jun 5, In : Sensors (Switzerland). 17, 6, 1289.

Research output: Contribution to journalArticle

11 Citations (Scopus)

R2-TSV: A repairable and reliable TSV set structure reutilizing redundancies

Park, J., Cheong, M. & Kang, S., 2017 Jun, In : IEEE Transactions on Reliability. 66, 2, p. 458-466 9 p., 2681103.

Research output: Contribution to journalArticle

9 Citations (Scopus)

Reconfigurable scan architecture for test power and data volume reduction

Oh, H., Kim, H., Lim, J. & Kang, S., 2017, In : ieice electronics express. 14, 13, 20170415.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Test access mechaism for stack test time reduction of 3-dimensional integrated circuit

Choi, I., Oh, H. & Kang, S., 2017 Jan 3, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., p. 522-525 4 p. 7804019. (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Test item priority estimation for high parallel test efficiency under ATE debug time constraints

Lee, Y. W., Choi, I., Oh, K. H., Ko, J. J. & Kang, S., 2017 Nov 3, ITC-Asia 2017 - International Test Conference in Asia. Institute of Electrical and Electronics Engineers Inc., p. 150-154 5 p. 8097131. (ITC-Asia 2017 - International Test Conference in Asia).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2016

A 2-D compaction method using macro block for post-silicon validation

Jung, W., Oh, H., Kang, D. & Kang, S., 2016 Feb 8, ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc., p. 41-42 2 p. 7401690. (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

A New 3-D Fuse Architecture to Improve Yield of 3-D Memories

Kang, W., Lee, C., Lim, H. & Kang, S., 2016 Oct, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35, 10, p. 1763-1767 5 p., 7395326.

Research output: Contribution to journalArticle

A new built-in redundancy analysis algorithm based on multiple memory blocks

Kim, J., Cho, K., Lee, W. & Kang, S., 2016 Feb 8, ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc., p. 43-44 2 p. 7401691. (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

A new in-field bad block detection scheme for NAND flash chips

Kang, D., Cho, K. & Kang, S., 2016 Feb 8, ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc., p. 69-70 2 p. 7401657. (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A scan segment skip technique for low power test

Lee, H., Lee, J., Lim, H. & Kang, S., 2016 Feb 8, ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc., p. 127-128 2 p. 7401669. (ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)