• 1159 Citations
  • 15 h-Index
1989 …2020

Research output per year

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2020

Efficient systolic-array redundancy architecture for offline/online repair

Cho, K., Lee, I., Lim, H. & Kang, S., 2020 Feb, In : Electronics (Switzerland). 9, 2, 338.

Research output: Contribution to journalArticle

Open Access

GPU-Based Redundancy Analysis Using Concurrent Evaluation

Kim, T. H., Lee, H. & Kang, S., 2020 Mar, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28, 3, p. 805-817 13 p., 8935214.

Research output: Contribution to journalArticle

2019

A low-cost concurrent TSV test architecture with lossless test output compression scheme

Lee, Y. W., Lim, H., Seo, S., Cho, K. & Kang, S., 2019 Aug 1, In : PloS one. 14, 8, e0221043.

Research output: Contribution to journalArticle

Open Access

An efficient BIRA utilizing characteristics of spare pivot faults

Cho, K., Lee, Y. W., Seo, S. & Kang, S., 2019 Mar, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38, 3, p. 551-561 11 p., 8323241.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Dynamic built-in redundancy analysis for memory repair

Lee, H., Han, D., Lee, S. & Kang, S., 2019 Oct, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27, 10, p. 2365-2374 10 p., 8746162.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Highly reliable redundant TSV architecture for clustered faults

Lee, I., Cheong, M. & Kang, S., 2019 Mar, In : IEEE Transactions on Reliability. 68, 1, p. 237-247 11 p., 8444082.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Test-Friendly Data-Selectable Self-Gating (DSSG)

Kim, J., Lee, S. & Kang, S., 2019 Aug, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27, 8, p. 1972-1976 5 p., 8728193.

Research output: Contribution to journalArticle

TSV repair architecture for clustered faults

Jang, J., Cheong, M. & Kang, S., 2019 Jan, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38, 1, p. 190-194 5 p., 8299466.

Research output: Contribution to journalArticle

2018

A debug scheme to improve the error identification in post-silicon validation

Choi, I., Jung, W., Oh, H. & Kang, S., 2018 Sep, In : PloS one. 13, 9, e0202216.

Research output: Contribution to journalArticle

1 Citation (Scopus)

An area-efficient BIRA with 1-D spare segments

Kim, D., Lee, H. & Kang, S., 2018 Jan, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26, 1, p. 206-210 5 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

A Statistic-Based Scan Chain Reordering for Energy-Quality Scalable Scan Test

Seo, S., Cho, K., Lee, Y. W. & Kang, S., 2018 Sep, In : IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 8, 3, p. 391-403 13 p., 8355813.

Research output: Contribution to journalArticle

1 Citation (Scopus)
1 Citation (Scopus)

Test resource reused debug scheme to reduce the post-silicon debug cost

Choi, I., Oh, H., Lee, Y. W. & Kang, S., 2018 Dec 1, In : IEEE Transactions on Computers. 67, 12, p. 1835-1839 5 p., 8359333.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Thermal aware test scheduling for NTV circuit

Lim, J., Oh, H., Kim, H. & Kang, S., 2018 Apr, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 37, 4, p. 906-910 5 p., 7984890.

Research output: Contribution to journalArticle

1 Citation (Scopus)
2017

A low-cost DAC BIST structure using a resistor loop

Jang, J., Kim, H. & Kang, S., 2017 Feb, In : PloS one. 12, 2, e0172331.

Research output: Contribution to journalArticle

An on-chip error detection method to reduce the post-silicon debug time

Oh, H., Han, T., Choi, I. & Kang, S., 2017 Jan 1, In : IEEE Transactions on Computers. 66, 1, p. 38-44 7 p., 7464321.

Research output: Contribution to journalArticle

5 Citations (Scopus)

A novel X-filling method for capture power reduction

Kim, H., Oh, H., Lim, J. & Kang, S., 2017, In : ieice electronics express. 14, 23, 20171093.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation

Jang, J., Cheong, M., Ahn, J. H., Lim, S. K. & Kang, S., 2017 Mar, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 3, p. 1178-1182 5 p., 7747508.

Research output: Contribution to journalArticle

1 Citation (Scopus)

DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores

Oh, H., Choi, I. & Kang, S., 2017 Sep 1, In : IEEE Transactions on Computers. 66, 9, p. 1504-1517 14 p., 7872459.

Research output: Contribution to journalArticle

5 Citations (Scopus)

Dynamic voltage frequency scaling-aware refresh management for 3D DRAM over processor architecture

Lim, J., Kim, H., Oh, H. & Kang, S., 2017 Jul 6, In : Electronics Letters. 53, 14, p. 910-912 3 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

FRESH: A New Test Result Extraction Scheme for Fast TSV Tests

Park, J., Lim, H. & Kang, S., 2017 Feb, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36, 2, p. 336-345 10 p., 7488276.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs

Lee, Y. W., Lim, H. & Kang, S., 2017 Oct, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36, 10, p. 1759-1763 5 p., 7572121.

Research output: Contribution to journalArticle

4 Citations (Scopus)

Hardware-Efficient Built-In Redundancy Analysis for Memory with Various Spares

Kim, J., Lee, W., Cho, K. & Kang, S., 2017 Mar, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 3, p. 844-856 13 p., 7572978.

Research output: Contribution to journalArticle

10 Citations (Scopus)

Low cost endurance test-pattern generation for multi-level cell flash memory

Cha, J., Cho, K., Yu, S. & Kang, S., 2017 Feb, In : Journal of Semiconductor Technology and Science. 17, 1, p. 147-155 9 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

Proof of concept of home IoT connected vehicles

Kim, Y., Oh, H. & Kang, S., 2017 Jun 5, In : Sensors (Switzerland). 17, 6, 1289.

Research output: Contribution to journalArticle

11 Citations (Scopus)

R2-TSV: A repairable and reliable TSV set structure reutilizing redundancies

Park, J., Cheong, M. & Kang, S., 2017 Jun, In : IEEE Transactions on Reliability. 66, 2, p. 458-466 9 p., 2681103.

Research output: Contribution to journalArticle

9 Citations (Scopus)

Reconfigurable scan architecture for test power and data volume reduction

Oh, H., Kim, H., Lim, J. & Kang, S., 2017, In : ieice electronics express. 14, 13, 20170415.

Research output: Contribution to journalArticle

1 Citation (Scopus)
2016

A New 3-D Fuse Architecture to Improve Yield of 3-D Memories

Kang, W., Lee, C., Lim, H. & Kang, S., 2016 Oct, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35, 10, p. 1763-1767 5 p., 7395326.

Research output: Contribution to journalArticle

A survey of repair analysis algorithms for memories

Cho, K., Kang, W., Cho, H., Lee, C. & Kang, S., 2016 Oct, In : ACM Computing Surveys. 49, 3, 47.

Research output: Contribution to journalArticle

6 Citations (Scopus)

Optimized Built-In Self-Repair for Multiple Memories

Kang, W., Lee, C., Lim, H. & Kang, S., 2016 Jun, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24, 6, p. 2174-2183 10 p., 7349243.

Research output: Contribution to journalArticle

5 Citations (Scopus)

Parallelized Network-on-Chip-Reused Test Access Mechanism for Multiple Identical Cores

Han, T., Choi, I., Oh, H. & Kang, S., 2016 Jul, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35, 7, p. 1219-1223 5 p., 7275127.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Tri-State Coding Using Reconfiguration of Twisted Ring Counter for Test Data Compression

Seo, S., Lee, Y. & Kang, S., 2016 Feb, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35, 2, p. 274-284 11 p., 7061468.

Research output: Contribution to journalArticle

6 Citations (Scopus)
2015

3-D Stacked DRAM Refresh Management with Guaranteed Data Reliability

Lim, J., Lim, H. & Kang, S., 2015 Sep 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 34, 9, p. 1455-1466 12 p., 7061398.

Research output: Contribution to journalArticle

4 Citations (Scopus)

A 3 dimensional built-in self-repair scheme for yield improvement of 3 dimensional memories

Kang, W., Lee, C., Lim, H. & Kang, S., 2015 Jun 1, In : IEEE Transactions on Reliability. 64, 2, p. 586-595 10 p., 7061513.

Research output: Contribution to journalArticle

14 Citations (Scopus)

A New Accelerated Endurance Test for Terabit NAND Flash Memory Using Interference Effect

Cha, J., Kang, W., Chung, J., Park, K. & Kang, S., 2015 Aug 1, In : IEEE Transactions on Semiconductor Manufacturing. 28, 3, p. 399-407 9 p., 7101285.

Research output: Contribution to journalArticle

2 Citations (Scopus)

A novel massively parallel testing method using multi-root for high reliability

Kim, H., Lee, Y. & Kang, S., 2015 Mar 1, In : IEEE Transactions on Reliability. 64, 1, p. 486-496 11 p., 6872606.

Research output: Contribution to journalArticle

7 Citations (Scopus)

Eco assist techniques through real-time monitoring of BEv energy usage efficiency

Kim, Y., Lee, I. & Kang, S., 2015 Jun 25, In : Sensors (Switzerland). 15, 7, p. 14946-14959 14 p.

Research output: Contribution to journalArticle

4 Citations (Scopus)

Fully programmable memory BIST for commodity DRAMs

Kim, I., Jeong, W., Kang, D. & Kang, S., 2015 Aug 1, In : ETRI Journal. 37, 4, p. 787-792 6 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Histogram-based calibration method for pipeline ADCs

Son, H., Jang, J., Kim, H. & Kang, S., 2015 Jun 12, In : PloS one. 10, 6, e0129736.

Research output: Contribution to journalArticle

Lifetime reliability enhancement of microprocessors: Mitigating the impact of negative bias temperature instability

Hong, H., Lim, J., Lim, H. & Kang, S., 2015 Sep 1, In : ACM Computing Surveys. 48, 1, 9.

Research output: Contribution to journalArticle

9 Citations (Scopus)

Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores

Han, T., Choi, I. & Kang, S., 2015 Aug 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23, 8, p. 1439-1447 9 p., 6871421.

Research output: Contribution to journalArticle

2 Citations (Scopus)

Multi-operation-based constrained random verification for on-chip memory

Son, H., Jang, J., Kim, H. & Kang, S., 2015 Jun 1, In : Journal of Semiconductor Technology and Science. 15, 3, p. 423-426 4 p.

Research output: Contribution to journalArticle

New thermal-aware voltage Island formation for 3D many-core processors

Hong, H., Lim, J., Lim, H. & Kang, S., 2015 Feb 1, In : ETRI Journal. 37, 1, p. 118-127 10 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Reduced-code test method using sub-histograms for pipelined ADCs

Son, H., Jang, J., Kim, H. & Kang, S., 2015 Jun 25, In : ieice electronics express. 12, 12, p. 1-10 10 p., 20150417.

Research output: Contribution to journalArticle

2014

A BIRA for memories with an optimal repair rate using spare memories for area reduction

Kang, W., Cho, H., Lee, J. & Kang, S., 2014 Nov 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22, 11, p. 2336-2349 14 p., 6663698.

Research output: Contribution to journalArticle

15 Citations (Scopus)

A delay test architecture for TSV with resistive open defects in 3-D stacked memories

Sung, H., Cho, K., Yoon, K. & Kang, S., 2014 Nov 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22, 11, p. 2380-2387 8 p., 6674065.

Research output: Contribution to journalArticle

14 Citations (Scopus)

A new fuse architecture and a new post-share redundancy scheme for yield enhancement in 3-D-stacked memories

Lee, C., Kang, W., Cho, D. & Kang, S., 2014 May, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 33, 5, p. 786-797 12 p., 6800196.

Research output: Contribution to journalArticle

11 Citations (Scopus)

A new multi-site test for system-on-chip using multi-site star test architecture

Han, D., Lee, Y. & Kang, S., 2014 Apr, In : ETRI Journal. 36, 2, p. 293-300 8 p.

Research output: Contribution to journalArticle

4 Citations (Scopus)

A novel test access mechanism for parallel testing of multi-core system

Han, T., Choi, I. & Kang, S., 2014 Mar 6, In : ieice electronics express. 11, 6, 20140093.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Interleaving test algorithm for subthreshold leakage-current defects in DRAM considering the equal bit line stress

Shin, H., Park, Y., Lee, G., Park, J. & Kang, S., 2014 Apr, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22, 4, p. 803-812 10 p., 6514723.

Research output: Contribution to journalArticle

2 Citations (Scopus)