1 Gbit SDRAM with an independent sub-array controlled scheme and a hierarchical decoding scheme

K. C. Lee, Hong Il Yoon, S. B. Lee, J. H. Lee, B. S. Moon, K. Y. Kim, C. H. Kim, S. I. Cho

Research output: Contribution to conferencePaper

5 Citations (Scopus)

Abstract

A prototype 1 Gbit synchronous dynamic random access memory (SDRAM) with independent array controlled isolation and decoding schemes is demonstrated. A fully working device with a size of 570 mm2 is fabricated using a 0.16 μm CMOS process. The design techniques utilizing the independent sub-array controlled scheme and the hierarchical decoding scheme to achieve enhanced failure analysis, lower power consumption, and smaller chip size, are presented.

Original languageEnglish
Pages103-104
Number of pages2
Publication statusPublished - 1997 Dec 1
EventProceedings of the 1997 Symposium on VLSI Circuits - Kyoto, Jpn
Duration: 1997 Jun 121997 Jun 14

Other

OtherProceedings of the 1997 Symposium on VLSI Circuits
CityKyoto, Jpn
Period97/6/1297/6/14

Fingerprint

Decoding
Data storage equipment
Failure analysis
Electric power utilization

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Lee, K. C., Yoon, H. I., Lee, S. B., Lee, J. H., Moon, B. S., Kim, K. Y., ... Cho, S. I. (1997). 1 Gbit SDRAM with an independent sub-array controlled scheme and a hierarchical decoding scheme. 103-104. Paper presented at Proceedings of the 1997 Symposium on VLSI Circuits, Kyoto, Jpn, .
Lee, K. C. ; Yoon, Hong Il ; Lee, S. B. ; Lee, J. H. ; Moon, B. S. ; Kim, K. Y. ; Kim, C. H. ; Cho, S. I. / 1 Gbit SDRAM with an independent sub-array controlled scheme and a hierarchical decoding scheme. Paper presented at Proceedings of the 1997 Symposium on VLSI Circuits, Kyoto, Jpn, .2 p.
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title = "1 Gbit SDRAM with an independent sub-array controlled scheme and a hierarchical decoding scheme",
abstract = "A prototype 1 Gbit synchronous dynamic random access memory (SDRAM) with independent array controlled isolation and decoding schemes is demonstrated. A fully working device with a size of 570 mm2 is fabricated using a 0.16 μm CMOS process. The design techniques utilizing the independent sub-array controlled scheme and the hierarchical decoding scheme to achieve enhanced failure analysis, lower power consumption, and smaller chip size, are presented.",
author = "Lee, {K. C.} and Yoon, {Hong Il} and Lee, {S. B.} and Lee, {J. H.} and Moon, {B. S.} and Kim, {K. Y.} and Kim, {C. H.} and Cho, {S. I.}",
year = "1997",
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language = "English",
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note = "Proceedings of the 1997 Symposium on VLSI Circuits ; Conference date: 12-06-1997 Through 14-06-1997",

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Lee, KC, Yoon, HI, Lee, SB, Lee, JH, Moon, BS, Kim, KY, Kim, CH & Cho, SI 1997, '1 Gbit SDRAM with an independent sub-array controlled scheme and a hierarchical decoding scheme' Paper presented at Proceedings of the 1997 Symposium on VLSI Circuits, Kyoto, Jpn, 97/6/12 - 97/6/14, pp. 103-104.

1 Gbit SDRAM with an independent sub-array controlled scheme and a hierarchical decoding scheme. / Lee, K. C.; Yoon, Hong Il; Lee, S. B.; Lee, J. H.; Moon, B. S.; Kim, K. Y.; Kim, C. H.; Cho, S. I.

1997. 103-104 Paper presented at Proceedings of the 1997 Symposium on VLSI Circuits, Kyoto, Jpn, .

Research output: Contribution to conferencePaper

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AU - Lee, K. C.

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AU - Moon, B. S.

AU - Kim, K. Y.

AU - Kim, C. H.

AU - Cho, S. I.

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N2 - A prototype 1 Gbit synchronous dynamic random access memory (SDRAM) with independent array controlled isolation and decoding schemes is demonstrated. A fully working device with a size of 570 mm2 is fabricated using a 0.16 μm CMOS process. The design techniques utilizing the independent sub-array controlled scheme and the hierarchical decoding scheme to achieve enhanced failure analysis, lower power consumption, and smaller chip size, are presented.

AB - A prototype 1 Gbit synchronous dynamic random access memory (SDRAM) with independent array controlled isolation and decoding schemes is demonstrated. A fully working device with a size of 570 mm2 is fabricated using a 0.16 μm CMOS process. The design techniques utilizing the independent sub-array controlled scheme and the hierarchical decoding scheme to achieve enhanced failure analysis, lower power consumption, and smaller chip size, are presented.

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Lee KC, Yoon HI, Lee SB, Lee JH, Moon BS, Kim KY et al. 1 Gbit SDRAM with an independent sub-array controlled scheme and a hierarchical decoding scheme. 1997. Paper presented at Proceedings of the 1997 Symposium on VLSI Circuits, Kyoto, Jpn, .