1 Gbit SDRAM with an independent sub-array controlled scheme and a hierarchical decoding scheme

K. C. Lee, H. Yoon, S. B. Lee, J. H. Lee, B. S. Moon, K. Y. Kim, C. H. Kim, S. I. Cho

Research output: Contribution to conferencePaper

5 Citations (Scopus)

Abstract

A prototype 1 Gbit synchronous dynamic random access memory (SDRAM) with independent array controlled isolation and decoding schemes is demonstrated. A fully working device with a size of 570 mm2 is fabricated using a 0.16 μm CMOS process. The design techniques utilizing the independent sub-array controlled scheme and the hierarchical decoding scheme to achieve enhanced failure analysis, lower power consumption, and smaller chip size, are presented.

Original languageEnglish
Pages103-104
Number of pages2
Publication statusPublished - 1997 Dec 1
EventProceedings of the 1997 Symposium on VLSI Circuits - Kyoto, Jpn
Duration: 1997 Jun 121997 Jun 14

Other

OtherProceedings of the 1997 Symposium on VLSI Circuits
CityKyoto, Jpn
Period97/6/1297/6/14

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Lee, K. C., Yoon, H., Lee, S. B., Lee, J. H., Moon, B. S., Kim, K. Y., Kim, C. H., & Cho, S. I. (1997). 1 Gbit SDRAM with an independent sub-array controlled scheme and a hierarchical decoding scheme. 103-104. Paper presented at Proceedings of the 1997 Symposium on VLSI Circuits, Kyoto, Jpn, .