1-Gb/s mixed-mode bpsk demodulator using a half-rate linear phase detector for 60-ghz wireless pan applications

Kwang Chun Choi, Duho Kim, Minsu Ko, Woo Young Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

A mixed-mode high-speed binary phase-shift keying (BPSK) demodulator for IEEE802.15.3c mm-wave wireless personal area network (WPAN) application is realized with 18μm CMOS process. The demodulator core consumes 23.4 mW from 1.8 V power supply while the chip area is 165 x 110 μm2. The power-consumption is less than that of the conventional BPSK demodulators and the chip-size is smaller. The proposed circuit is verified by 1-meter 60-GHz wireless link tests with 1-Gb/s data.

Original languageEnglish
Title of host publicationProceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Pages357-360
Number of pages4
DOIs
Publication statusPublished - 2008 Dec 1
Event2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan
Duration: 2008 Nov 32008 Nov 5

Publication series

NameProceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Other

Other2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
CountryJapan
CityFukuoka
Period08/11/308/11/5

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Choi, K. C., Kim, D., Ko, M., & Choi, W. Y. (2008). 1-Gb/s mixed-mode bpsk demodulator using a half-rate linear phase detector for 60-ghz wireless pan applications. In Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 (pp. 357-360). [4708801] (Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008). https://doi.org/10.1109/ASSCC.2008.4708801