10-Gb/s 850-nm CMOS OEIC receiver with a silicon avalanche photodetector

Jin Sung Youn, Myung Jae Lee, Kang Yeob Park, Woo Young Choi

Research output: Contribution to journalArticle

56 Citations (Scopus)


We present a 10-Gb/s optoelectronic integrated circuit (OEIC) receiver fabricated with standard 0.13-μm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. The OEIC receiver consists of a CMOS-compatible avalanche photodetector (CMOS-APD), a transimpedance amplifier (TIA), an offset cancellation network, a variable equalizer (EQ), a limiting amplifier (LA), and an output buffer. The CMOS-APD provides high responsivity as well as large photodetection bandwidth. The TIA is composed of two-stage differential amplifiers with high feedback resistance of 4 kΩ. The EQ compensates high-frequency loss by controlling the boosting gain with a capacitor array. The LA consists of five-stage gain cells with active feedback and negative capacitance to achieve broadband performance. With the OEIC receiver, we successfully demonstrate transmission of 10-Gb/s optical data at 850 nm with a bit error rate of 10 -12 at the incident optical power of 4-dBm. The OEIC receiver has the core chip area of about 0.26 mm 2 and consumes about 66.8 mW.

Original languageEnglish
Article number6032702
Pages (from-to)229-236
Number of pages8
JournalIEEE Journal of Quantum Electronics
Issue number2
Publication statusPublished - 2012 Feb 1

All Science Journal Classification (ASJC) codes

  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of '10-Gb/s 850-nm CMOS OEIC receiver with a silicon avalanche photodetector'. Together they form a unique fingerprint.

  • Cite this