An area- and power-efficient analogue adaptive equaliser (AEQ) is realised in a 0.13m CMOS technology. The negative capacitance circuits are exploited at the equalisation filter to achieve wider bandwidth and larger high-frequency boosting, instead of using passive inductors that lead to a large chip area. Measured results demonstrate the data rate of 10Gbit/s for 20 and 34inch FR4 traces as channels, while dissipating only 6mW from a single 1.2V supply. The chip core occupies an extremely small area of 50×130m2. To the best of the authors' knowledge, this chip achieves the lowest power consumption and the smallest chip area among the recently reported AEQs.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering