10Gbit/s 0.0065mm2 6mW analogue adaptive equaliser utilising negative capacitance

D. Lee, J. Han, G. Han, S. M. Park

Research output: Contribution to journalArticle

19 Citations (Scopus)

Abstract

An area- and power-efficient analogue adaptive equaliser (AEQ) is realised in a 0.13m CMOS technology. The negative capacitance circuits are exploited at the equalisation filter to achieve wider bandwidth and larger high-frequency boosting, instead of using passive inductors that lead to a large chip area. Measured results demonstrate the data rate of 10Gbit/s for 20 and 34inch FR4 traces as channels, while dissipating only 6mW from a single 1.2V supply. The chip core occupies an extremely small area of 50×130m2. To the best of the authors' knowledge, this chip achieves the lowest power consumption and the smallest chip area among the recently reported AEQs.

Original languageEnglish
Pages (from-to)863-865
Number of pages3
JournalElectronics Letters
Volume45
Issue number17
DOIs
Publication statusPublished - 2009 Aug 24

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Equalizers
Electric power utilization
Capacitance
Bandwidth
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Lee, D. ; Han, J. ; Han, G. ; Park, S. M. / 10Gbit/s 0.0065mm2 6mW analogue adaptive equaliser utilising negative capacitance. In: Electronics Letters. 2009 ; Vol. 45, No. 17. pp. 863-865.
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10Gbit/s 0.0065mm2 6mW analogue adaptive equaliser utilising negative capacitance. / Lee, D.; Han, J.; Han, G.; Park, S. M.

In: Electronics Letters, Vol. 45, No. 17, 24.08.2009, p. 863-865.

Research output: Contribution to journalArticle

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