1.25/2.5-Gb/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18-μm CMOS

Pyung Su Han, Woo-Young Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated-oscillators to align clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated-oscillator reset-phase control scheme alters the starting phase of gated-oscillators repeatedly between 0° and 180° according to the current clock phase. A prototype chip was designed with 0.18-μm CMOS technology and 1.25/2.5-Gb/s dual-mode operation was verified in measurement.

Original languageEnglish
Title of host publicationISCAS 2006
Subtitle of host publication2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages3069-3072
Number of pages4
Publication statusPublished - 2006 Dec 1
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
Duration: 2006 May 212006 May 24

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

OtherISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
CountryGreece
CityKos
Period06/5/2106/5/24

Fingerprint

Clocks
Recovery
Networks (circuits)
Phase control
Throughput

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Han, P. S., & Choi, W-Y. (2006). 1.25/2.5-Gb/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18-μm CMOS. In ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings (pp. 3069-3072). [1693273] (Proceedings - IEEE International Symposium on Circuits and Systems).
Han, Pyung Su ; Choi, Woo-Young. / 1.25/2.5-Gb/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18-μm CMOS. ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. pp. 3069-3072 (Proceedings - IEEE International Symposium on Circuits and Systems).
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abstract = "A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated-oscillators to align clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated-oscillator reset-phase control scheme alters the starting phase of gated-oscillators repeatedly between 0° and 180° according to the current clock phase. A prototype chip was designed with 0.18-μm CMOS technology and 1.25/2.5-Gb/s dual-mode operation was verified in measurement.",
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Han, PS & Choi, W-Y 2006, 1.25/2.5-Gb/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18-μm CMOS. in ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings., 1693273, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 3069-3072, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, 06/5/21.

1.25/2.5-Gb/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18-μm CMOS. / Han, Pyung Su; Choi, Woo-Young.

ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. p. 3069-3072 1693273 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AU - Choi, Woo-Young

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N2 - A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated-oscillators to align clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated-oscillator reset-phase control scheme alters the starting phase of gated-oscillators repeatedly between 0° and 180° according to the current clock phase. A prototype chip was designed with 0.18-μm CMOS technology and 1.25/2.5-Gb/s dual-mode operation was verified in measurement.

AB - A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated-oscillators to align clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated-oscillator reset-phase control scheme alters the starting phase of gated-oscillators repeatedly between 0° and 180° according to the current clock phase. A prototype chip was designed with 0.18-μm CMOS technology and 1.25/2.5-Gb/s dual-mode operation was verified in measurement.

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Han PS, Choi W-Y. 1.25/2.5-Gb/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18-μm CMOS. In ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. p. 3069-3072. 1693273. (Proceedings - IEEE International Symposium on Circuits and Systems).