A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated oscillators to align the clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated oscillator reset-phase control scheme causes the starting phase of gated oscillators to alternate repeatedly between 0° and 180° according to the current clock phase. A prototype chip was designed with the 0.18-μm CMOS technology, and a 1.25/2.5-Gb/s dual-mode operation was verified by measurement.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2007 Jan|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering