1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuits in 0.18-μm CMOS Technology

Pyung Su Han, Woo-Young Choi

Research output: Contribution to journalArticle

16 Citations (Scopus)

Abstract

A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated oscillators to align the clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated oscillator reset-phase control scheme causes the starting phase of gated oscillators to alternate repeatedly between 0° and 180° according to the current clock phase. A prototype chip was designed with the 0.18-μm CMOS technology, and a 1.25/2.5-Gb/s dual-mode operation was verified by measurement.

Original languageEnglish
Pages (from-to)38-42
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume54
Issue number1
DOIs
Publication statusPublished - 2007 Jan 1

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Clocks
Recovery
Networks (circuits)
Phase control
Throughput

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuits in 0.18-μm CMOS Technology. / Han, Pyung Su; Choi, Woo-Young.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 54, No. 1, 01.01.2007, p. 38-42.

Research output: Contribution to journalArticle

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