As memory densities have rapidly increased, memory testing and repairing processes are the major keys to prevent the decline in the yield. For redundancy analysis (RA), fail addresses should be extracted by the external automatic test equipment (ATE) and stored into the failure bitmap. However, full size of the failure bitmap can be a huge burden on the ATE costs. In order to reduce the storage size, this paper presents a new failure bitmap compression method. The proposed method marks all of the addresses of the line fault, so that repairing solutions can be easily decided. Experimental results show that the proposed compression method greatly reduces the size of failure bitmap while minimizing the failure data loss.
|Title of host publication||Proceedings - International SoC Design Conference 2018, ISOCC 2018|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|Publication status||Published - 2019 Feb 22|
|Event||15th International SoC Design Conference, ISOCC 2018 - Daegu, Korea, Republic of|
Duration: 2018 Nov 12 → 2018 Nov 15
|Name||Proceedings - International SoC Design Conference 2018, ISOCC 2018|
|Conference||15th International SoC Design Conference, ISOCC 2018|
|Country/Territory||Korea, Republic of|
|Period||18/11/12 → 18/11/15|
Bibliographical noteFunding Information:
This research was supported by the MOTIE(Ministry of Trade, Industry & Energy(10067813) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device.
ACKNOWLEDGMENT This research was supported by the MOTIE(Ministry of Trade, Industry & Energy(10067813) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device.
© 2018 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials