2-D Failure Bitmap Compression Using Line Fault Marking Method

Keewon Cho, Young Woo Lee, Sungyoul Seo, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As memory densities have rapidly increased, memory testing and repairing processes are the major keys to prevent the decline in the yield. For redundancy analysis (RA), fail addresses should be extracted by the external automatic test equipment (ATE) and stored into the failure bitmap. However, full size of the failure bitmap can be a huge burden on the ATE costs. In order to reduce the storage size, this paper presents a new failure bitmap compression method. The proposed method marks all of the addresses of the line fault, so that repairing solutions can be easily decided. Experimental results show that the proposed compression method greatly reduces the size of failure bitmap while minimizing the failure data loss.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2018, ISOCC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages21-22
Number of pages2
ISBN (Electronic)9781538679609
DOIs
Publication statusPublished - 2019 Feb 22
Event15th International SoC Design Conference, ISOCC 2018 - Daegu, Korea, Republic of
Duration: 2018 Nov 122018 Nov 15

Publication series

NameProceedings - International SoC Design Conference 2018, ISOCC 2018

Conference

Conference15th International SoC Design Conference, ISOCC 2018
CountryKorea, Republic of
CityDaegu
Period18/11/1218/11/15

Bibliographical note

Funding Information:
This research was supported by the MOTIE(Ministry of Trade, Industry & Energy(10067813) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device.

Funding Information:
ACKNOWLEDGMENT This research was supported by the MOTIE(Ministry of Trade, Industry & Energy(10067813) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device.

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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