This paper describes a new test pattern generator to increase fault coverage and a test pattern transferring method to reduce test time without large hardware overhead in the BIST structure. The new pattern generator uses a 2-level LFSR scheme in which inputs are varied and controlled by the counter output. An asynchronous internal clock generated by an internal ring-oscillator is used for fast test pattern transfer into the scan chain. The new 2-level LFSR scheme is verified by the HITEC fault simulator.
|Number of pages||4|
|Journal||Proceedings of the IEEE Great Lakes Symposium on VLSI|
|Publication status||Published - 2001|
|Event||11th Great Lakes Sysmposium on VLSI (GLSVLSI 2001) - West Lafayette, IN, United States|
Duration: 2001 Mar 22 → 2001 Mar 23
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering