2-Level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency built-in-self-test

S. M. Yoo, S. O. Jung, S. M. Kang

Research output: Contribution to journalConference article

1 Citation (Scopus)

Abstract

This paper describes a new test pattern generator to increase fault coverage and a test pattern transferring method to reduce test time without large hardware overhead in the BIST structure. The new pattern generator uses a 2-level LFSR scheme in which inputs are varied and controlled by the counter output. An asynchronous internal clock generated by an internal ring-oscillator is used for fast test pattern transfer into the scan chain. The new 2-level LFSR scheme is verified by the HITEC fault simulator.

Original languageEnglish
Pages (from-to)93-96
Number of pages4
JournalProceedings of the IEEE Great Lakes Symposium on VLSI
Publication statusPublished - 2001 Jan 1
Event11th Great Lakes Sysmposium on VLSI (GLSVLSI 2001) - West Lafayette, IN, United States
Duration: 2001 Mar 222001 Mar 23

Fingerprint

Built-in self test
Clocks
Simulators
Hardware
Costs

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

@article{df4fb92296e64cfcb0ced9411ec92243,
title = "2-Level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency built-in-self-test",
abstract = "This paper describes a new test pattern generator to increase fault coverage and a test pattern transferring method to reduce test time without large hardware overhead in the BIST structure. The new pattern generator uses a 2-level LFSR scheme in which inputs are varied and controlled by the counter output. An asynchronous internal clock generated by an internal ring-oscillator is used for fast test pattern transfer into the scan chain. The new 2-level LFSR scheme is verified by the HITEC fault simulator.",
author = "Yoo, {S. M.} and Jung, {S. O.} and Kang, {S. M.}",
year = "2001",
month = "1",
day = "1",
language = "English",
pages = "93--96",
journal = "Proceedings of the IEEE Great Lakes Symposium on VLSI",
issn = "1066-1395",
publisher = "IEEE Computer Society",

}

TY - JOUR

T1 - 2-Level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency built-in-self-test

AU - Yoo, S. M.

AU - Jung, S. O.

AU - Kang, S. M.

PY - 2001/1/1

Y1 - 2001/1/1

N2 - This paper describes a new test pattern generator to increase fault coverage and a test pattern transferring method to reduce test time without large hardware overhead in the BIST structure. The new pattern generator uses a 2-level LFSR scheme in which inputs are varied and controlled by the counter output. An asynchronous internal clock generated by an internal ring-oscillator is used for fast test pattern transfer into the scan chain. The new 2-level LFSR scheme is verified by the HITEC fault simulator.

AB - This paper describes a new test pattern generator to increase fault coverage and a test pattern transferring method to reduce test time without large hardware overhead in the BIST structure. The new pattern generator uses a 2-level LFSR scheme in which inputs are varied and controlled by the counter output. An asynchronous internal clock generated by an internal ring-oscillator is used for fast test pattern transfer into the scan chain. The new 2-level LFSR scheme is verified by the HITEC fault simulator.

UR - http://www.scopus.com/inward/record.url?scp=0034996831&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034996831&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0034996831

SP - 93

EP - 96

JO - Proceedings of the IEEE Great Lakes Symposium on VLSI

JF - Proceedings of the IEEE Great Lakes Symposium on VLSI

SN - 1066-1395

ER -