2-Level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency built-in-self-test

S. M. Yoo, S. O. Jung, S. M. Kang

Research output: Contribution to journalConference article

1 Citation (Scopus)


This paper describes a new test pattern generator to increase fault coverage and a test pattern transferring method to reduce test time without large hardware overhead in the BIST structure. The new pattern generator uses a 2-level LFSR scheme in which inputs are varied and controlled by the counter output. An asynchronous internal clock generated by an internal ring-oscillator is used for fast test pattern transfer into the scan chain. The new 2-level LFSR scheme is verified by the HITEC fault simulator.

Original languageEnglish
Pages (from-to)93-96
Number of pages4
JournalProceedings of the IEEE Great Lakes Symposium on VLSI
Publication statusPublished - 2001 Jan 1
Event11th Great Lakes Sysmposium on VLSI (GLSVLSI 2001) - West Lafayette, IN, United States
Duration: 2001 Mar 222001 Mar 23


All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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