25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections

Gyu Seob Jeong; Jeongho Hwang; Hong Seok Choi; Hyungrok Do; Daehyun Koh; Daeyoung Yun; Jinhyung Lee; Kwanseo Park; Han Gon Ko; Kwangho Lee; Jiho Joo; Gyungock Kim; Deog Kyoon Jeong

doi:10.1109/TCSII.2018.2850663

25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections

Gyu Seob Jeong, Jeongho Hwang, Hong Seok Choi, Hyungrok Do, Daehyun Koh, Daeyoung Yun, Jinhyung Lee, Kwanseo Park, Han Gon Ko, Kwangho Lee, Jiho Joo, Gyungock Kim, Deog Kyoon Jeong

School of System & Semiconductor Engineering

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

This brief presents a clocked pluggable optics suitable for high-density data center interconnections. The proposed architecture performs a SERDES function at the module side by exploiting a forwarded clock from the ASIC. Due to the relaxed channel loss of the ASIC-to-module interface, the use of power-hungry equalizers can be avoided. Based on an 850-nm multi-mode fiber interface, a 25-Gb/s link operation is demonstrated. A vertical-cavity surface-emitting laser-based transmitter outputs an optical modulation power of 0.6 mW. The optical receiver sensitivity is measured to be-7.5 dBm at 21.2 Gb/s with an optical excitation, and 120 μ A_pp at 25 Gb/s with an electrical excitation. The jitter tracking capability of the implemented clock and data recovery is evaluated in the presence of ±100-ppm frequency offsets and the measured jitter tolerance complies with the 100 GbE specification well. The optical transceiver is implemented in 65-nm CMOS technology and consumes 281 mW at 25 Gb/s, corresponding to the energy efficiency of 11.2 pJ/b.

Original language	English
Article number	8395366
Pages (from-to)	1395-1399
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	65
Issue number	10
DOIs	https://doi.org/10.1109/TCSII.2018.2850663
Publication status	Published - 2018 Oct

Bibliographical note

Funding Information:
Manuscript received June 7, 2018; accepted June 21, 2018. Date of publication June 25, 2018; date of current version September 27, 2018. This work was supported by the Electronics and Telecommunications Research Institute. This brief was recommended by Associate J. B. Begueret. (Corresponding author: Deog-Kyoon Jeong.) G.-S. Jeong, J. Hwang, H.-S. Choi, H. Do, D. Koh, D. Yun, J. Lee, K. Park, H.-G. Ko, K. Lee, and D.-K. Jeong are with the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea, and also with the Inter-University Semiconductor Research Center, Seoul National University, Seoul 08826, South Korea (e-mail: gsjeong@isdl.snu.ac.kr; dkjeong@snu.ac.kr).

Publisher Copyright:
© 2004-2012 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/TCSII.2018.2850663

Cite this

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title = "25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections",

abstract = "This brief presents a clocked pluggable optics suitable for high-density data center interconnections. The proposed architecture performs a SERDES function at the module side by exploiting a forwarded clock from the ASIC. Due to the relaxed channel loss of the ASIC-to-module interface, the use of power-hungry equalizers can be avoided. Based on an 850-nm multi-mode fiber interface, a 25-Gb/s link operation is demonstrated. A vertical-cavity surface-emitting laser-based transmitter outputs an optical modulation power of 0.6 mW. The optical receiver sensitivity is measured to be-7.5 dBm at 21.2 Gb/s with an optical excitation, and 120 μ App at 25 Gb/s with an electrical excitation. The jitter tracking capability of the implemented clock and data recovery is evaluated in the presence of ±100-ppm frequency offsets and the measured jitter tolerance complies with the 100 GbE specification well. The optical transceiver is implemented in 65-nm CMOS technology and consumes 281 mW at 25 Gb/s, corresponding to the energy efficiency of 11.2 pJ/b.",

author = "Jeong, {Gyu Seob} and Jeongho Hwang and Choi, {Hong Seok} and Hyungrok Do and Daehyun Koh and Daeyoung Yun and Jinhyung Lee and Kwanseo Park and Ko, {Han Gon} and Kwangho Lee and Jiho Joo and Gyungock Kim and Jeong, {Deog Kyoon}",

note = "Funding Information: Manuscript received June 7, 2018; accepted June 21, 2018. Date of publication June 25, 2018; date of current version September 27, 2018. This work was supported by the Electronics and Telecommunications Research Institute. This brief was recommended by Associate J. B. Begueret. (Corresponding author: Deog-Kyoon Jeong.) G.-S. Jeong, J. Hwang, H.-S. Choi, H. Do, D. Koh, D. Yun, J. Lee, K. Park, H.-G. Ko, K. Lee, and D.-K. Jeong are with the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea, and also with the Inter-University Semiconductor Research Center, Seoul National University, Seoul 08826, South Korea (e-mail: gsjeong@isdl.snu.ac.kr; dkjeong@snu.ac.kr). Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

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AU - Do, Hyungrok

AU - Koh, Daehyun

AU - Yun, Daeyoung

AU - Lee, Jinhyung

AU - Park, Kwanseo

AU - Ko, Han Gon

AU - Lee, Kwangho

AU - Joo, Jiho

AU - Kim, Gyungock

AU - Jeong, Deog Kyoon

N1 - Funding Information: Manuscript received June 7, 2018; accepted June 21, 2018. Date of publication June 25, 2018; date of current version September 27, 2018. This work was supported by the Electronics and Telecommunications Research Institute. This brief was recommended by Associate J. B. Begueret. (Corresponding author: Deog-Kyoon Jeong.) G.-S. Jeong, J. Hwang, H.-S. Choi, H. Do, D. Koh, D. Yun, J. Lee, K. Park, H.-G. Ko, K. Lee, and D.-K. Jeong are with the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea, and also with the Inter-University Semiconductor Research Center, Seoul National University, Seoul 08826, South Korea (e-mail: gsjeong@isdl.snu.ac.kr; dkjeong@snu.ac.kr). Publisher Copyright: © 2004-2012 IEEE.

PY - 2018/10

Y1 - 2018/10

N2 - This brief presents a clocked pluggable optics suitable for high-density data center interconnections. The proposed architecture performs a SERDES function at the module side by exploiting a forwarded clock from the ASIC. Due to the relaxed channel loss of the ASIC-to-module interface, the use of power-hungry equalizers can be avoided. Based on an 850-nm multi-mode fiber interface, a 25-Gb/s link operation is demonstrated. A vertical-cavity surface-emitting laser-based transmitter outputs an optical modulation power of 0.6 mW. The optical receiver sensitivity is measured to be-7.5 dBm at 21.2 Gb/s with an optical excitation, and 120 μ App at 25 Gb/s with an electrical excitation. The jitter tracking capability of the implemented clock and data recovery is evaluated in the presence of ±100-ppm frequency offsets and the measured jitter tolerance complies with the 100 GbE specification well. The optical transceiver is implemented in 65-nm CMOS technology and consumes 281 mW at 25 Gb/s, corresponding to the energy efficiency of 11.2 pJ/b.

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25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections

Abstract

Bibliographical note

All Science Journal Classification (ASJC) codes

UN SDGs

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