2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

Hongil Yoon, Gi Won Cha, Changsik Yoo, Nam Jong Kim, Keum Yong Kim, Chang Ho Lee, Kyu Nam Lim, Kyuchan Lee, Jun Young Jeon, Tae Sung Jung, Hongsik Jeong, Tae Young Chung, Kinam Kim, Soo In Cho

Research output: Contribution to journalArticle

20 Citations (Scopus)

Abstract

A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-μm process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated.

Original languageEnglish
Pages (from-to)1589-1599
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume34
Issue number11
DOIs
Publication statusPublished - 1999 Nov 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Yoon, H., Cha, G. W., Yoo, C., Kim, N. J., Kim, K. Y., Lee, C. H., Lim, K. N., Lee, K., Jeon, J. Y., Jung, T. S., Jeong, H., Chung, T. Y., Kim, K., & Cho, S. I. (1999). 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM. IEEE Journal of Solid-State Circuits, 34(11), 1589-1599. https://doi.org/10.1109/4.799867