3.37 μw/Ch modular scalable neural recording system with embedded lossless compression for dynamic power reduction

Sung Yun Park; Jihyun Cho; Euisik Yoon

doi:10.23919/VLSIC.2017.8008468

3.37 μw/Ch modular scalable neural recording system with embedded lossless compression for dynamic power reduction

Sung Yun Park, Jihyun Cho, Euisik Yoon

Yonsei Advanced Science Institute

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

We report a neural recording system with embedded lossless compression using spatiotemporal correlation and sparsity of neural signals to reduce dynamic power (P_d) dissipation for data transmission in high-density neural recording systems. We could successfully compress the data rate of neural signals by a factor of 5.35 (local field potential, LFP) and 10.54 (action potential, AP), respectively. Consequently we reduced Pd consumption by 89% while achieving the state-of-the-art recording performance of 3.37 μW/Ch, 5.18 μV_rms input-referred noise, and 3.41NEF²Vdd.

Original language	English
Title of host publication	2017 Symposium on VLSI Circuits, VLSI Circuits 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C168-C169
ISBN (Electronic)	9784863486065
DOIs	https://doi.org/10.23919/VLSIC.2017.8008468
Publication status	Published - 2017 Aug 10
Event	31st Symposium on VLSI Circuits, VLSI Circuits 2017 - Kyoto, Japan Duration: 2017 Jun 5 → 2017 Jun 8

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	31st Symposium on VLSI Circuits, VLSI Circuits 2017
Country	Japan
City	Kyoto
Period	17/6/5 → 17/6/8

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.23919/VLSIC.2017.8008468

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Park, S. Y., Cho, J., & Yoon, E. (2017). 3.37 μw/Ch modular scalable neural recording system with embedded lossless compression for dynamic power reduction. In 2017 Symposium on VLSI Circuits, VLSI Circuits 2017 (pp. C168-C169). [8008468] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIC.2017.8008468

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abstract = "We report a neural recording system with embedded lossless compression using spatiotemporal correlation and sparsity of neural signals to reduce dynamic power (Pd) dissipation for data transmission in high-density neural recording systems. We could successfully compress the data rate of neural signals by a factor of 5.35 (local field potential, LFP) and 10.54 (action potential, AP), respectively. Consequently we reduced Pd consumption by 89% while achieving the state-of-the-art recording performance of 3.37 μW/Ch, 5.18 μVrms input-referred noise, and 3.41NEF2Vdd.",

author = "Park, {Sung Yun} and Jihyun Cho and Euisik Yoon",

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Park, SY, Cho, J & Yoon, E 2017, 3.37 μw/Ch modular scalable neural recording system with embedded lossless compression for dynamic power reduction. in 2017 Symposium on VLSI Circuits, VLSI Circuits 2017., 8008468, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Institute of Electrical and Electronics Engineers Inc., pp. C168-C169, 31st Symposium on VLSI Circuits, VLSI Circuits 2017, Kyoto, Japan, 17/6/5. https://doi.org/10.23919/VLSIC.2017.8008468

3.37 μw/Ch modular scalable neural recording system with embedded lossless compression for dynamic power reduction. / Park, Sung Yun; Cho, Jihyun; Yoon, Euisik.

2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. C168-C169 8008468 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - We report a neural recording system with embedded lossless compression using spatiotemporal correlation and sparsity of neural signals to reduce dynamic power (Pd) dissipation for data transmission in high-density neural recording systems. We could successfully compress the data rate of neural signals by a factor of 5.35 (local field potential, LFP) and 10.54 (action potential, AP), respectively. Consequently we reduced Pd consumption by 89% while achieving the state-of-the-art recording performance of 3.37 μW/Ch, 5.18 μVrms input-referred noise, and 3.41NEF2Vdd.

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Park SY, Cho J, Yoon E. 3.37 μw/Ch modular scalable neural recording system with embedded lossless compression for dynamic power reduction. In 2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. C168-C169. 8008468. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.23919/VLSIC.2017.8008468