3.37 μw/Ch modular scalable neural recording system with embedded lossless compression for dynamic power reduction

Sung Yun Park, Jihyun Cho, Euisik Yoon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

We report a neural recording system with embedded lossless compression using spatiotemporal correlation and sparsity of neural signals to reduce dynamic power (Pd) dissipation for data transmission in high-density neural recording systems. We could successfully compress the data rate of neural signals by a factor of 5.35 (local field potential, LFP) and 10.54 (action potential, AP), respectively. Consequently we reduced Pd consumption by 89% while achieving the state-of-the-art recording performance of 3.37 μW/Ch, 5.18 μVrms input-referred noise, and 3.41NEF2Vdd.

Original languageEnglish
Title of host publication2017 Symposium on VLSI Circuits, VLSI Circuits 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesC168-C169
ISBN (Electronic)9784863486065
DOIs
Publication statusPublished - 2017 Aug 10
Event31st Symposium on VLSI Circuits, VLSI Circuits 2017 - Kyoto, Japan
Duration: 2017 Jun 52017 Jun 8

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other31st Symposium on VLSI Circuits, VLSI Circuits 2017
CountryJapan
CityKyoto
Period17/6/517/6/8

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Park, S. Y., Cho, J., & Yoon, E. (2017). 3.37 μw/Ch modular scalable neural recording system with embedded lossless compression for dynamic power reduction. In 2017 Symposium on VLSI Circuits, VLSI Circuits 2017 (pp. C168-C169). [8008468] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIC.2017.8008468