The demand for high-frame-rate CMOS image sensors is steadily increasing. Column-parallel single-slope (SS) ADCs are widely used in CMOS image sensors, because they can be implemented with small area, low noise, and high energy efficiency. To achieve high frame rate and low noise simultaneously, several techniques using SS ADCs, such as parallel multiple sampling , , dual-gain slopes , and dual-gain amplifiers , have been investigated. However, since the clock frequency of the SS ADC is already in the GHz range, it is very challenging to maintain energy efficiency as the frame rate increases further.
|Title of host publication||2019 IEEE International Solid-State Circuits Conference, ISSCC 2019|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|Publication status||Published - 2019 Mar 6|
|Event||2019 IEEE International Solid-State Circuits Conference, ISSCC 2019 - San Francisco, United States|
Duration: 2019 Feb 17 → 2019 Feb 21
|Name||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|Conference||2019 IEEE International Solid-State Circuits Conference, ISSCC 2019|
|Period||19/2/17 → 19/2/21|
Bibliographical noteFunding Information:
This work was supported by Samsung Research Funding & Incubation Center of Samsung Electronics under Project Number SRFC-IT1701-08
© 2019 IEEE.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering