7.7 Gbps encoder design for IEEE 802.11ac QC-LDPC codes

Yong Min Jung, Chul Ho Chung, Yun Ho Jung, Jae Seok Kim

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

This paper proposes a high-throughput encoding process and encoder architecture for quasicyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.

Original languageEnglish
Pages (from-to)419-426
Number of pages8
JournalJournal of Semiconductor Technology and Science
Volume14
Issue number4
DOIs
Publication statusPublished - 2014

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Throughput
Clocks
Hardware
Processing

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Jung, Yong Min ; Chung, Chul Ho ; Jung, Yun Ho ; Kim, Jae Seok. / 7.7 Gbps encoder design for IEEE 802.11ac QC-LDPC codes. In: Journal of Semiconductor Technology and Science. 2014 ; Vol. 14, No. 4. pp. 419-426.
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7.7 Gbps encoder design for IEEE 802.11ac QC-LDPC codes. / Jung, Yong Min; Chung, Chul Ho; Jung, Yun Ho; Kim, Jae Seok.

In: Journal of Semiconductor Technology and Science, Vol. 14, No. 4, 2014, p. 419-426.

Research output: Contribution to journalArticle

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