7.7Gbps encoder design for IEEE 802.11n/ac QC-LDPC codes

Yongmin Jung, Chulho Chung, Jaeseok Kim, Yunho Jung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

This paper proposes a high throughput encoding process and encoder architecture for quasi-cyclic low-density parity-check (QC-LDPC) codes in IEEE 802.11n/ac standards. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoder throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.

Original languageEnglish
Title of host publicationISOCC 2012 - 2012 International SoC Design Conference
Pages215-218
Number of pages4
DOIs
Publication statusPublished - 2012 Dec 1
Event2012 International SoC Design Conference, ISOCC 2012 - Jeju Island, Korea, Republic of
Duration: 2012 Nov 42012 Nov 7

Publication series

NameISOCC 2012 - 2012 International SoC Design Conference

Other

Other2012 International SoC Design Conference, ISOCC 2012
CountryKorea, Republic of
CityJeju Island
Period12/11/412/11/7

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All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Jung, Y., Chung, C., Kim, J., & Jung, Y. (2012). 7.7Gbps encoder design for IEEE 802.11n/ac QC-LDPC codes. In ISOCC 2012 - 2012 International SoC Design Conference (pp. 215-218). [6407078] (ISOCC 2012 - 2012 International SoC Design Conference). https://doi.org/10.1109/ISOCC.2012.6407078