This paper presents an impedance monitoring IC that achieves small area and wide DR. The stimulated signal is encoded by using pulse width modulation (PWM) and complex impedance can be measured by in- (I) and quadrature- (Q) phase outputs through dual phase demodulation. The two-level I/Q signals drive two gated-ring-oscillator (GRO) based ADCs, thus eliminating the distortion of GROs. Fabricated in 0.11μm CMOS, the prototype IC occupies only 0.02mm2. It achieves a wide DR of 100dB and a resolution of 19.21Ωrms at 1MΩ resistance in a conversion time of 5ms, and consumes 152.3μW. It corresponds to state-of-the-art resolution FoM of 14.6pJ/step.
|Title of host publication||2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2019 Jun|
|Event||33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan|
Duration: 2019 Jun 9 → 2019 Jun 14
|Name||IEEE Symposium on VLSI Circuits, Digest of Technical Papers|
|Conference||33rd Symposium on VLSI Circuits, VLSI Circuits 2019|
|Period||19/6/9 → 19/6/14|
Bibliographical noteFunding Information:
This research was supported by SK Hynix and the NRF of Korea (2018M3C7A1024654). Authors would like to thank the Rohde & Schwarz for test instruments.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering