Abstract
This paper presents an impedance monitoring IC that achieves small area and wide DR. The stimulated signal is encoded by using pulse width modulation (PWM) and complex impedance can be measured by in- (I) and quadrature- (Q) phase outputs through dual phase demodulation. The two-level I/Q signals drive two gated-ring-oscillator (GRO) based ADCs, thus eliminating the distortion of GROs. Fabricated in 0.11μm CMOS, the prototype IC occupies only 0.02mm2. It achieves a wide DR of 100dB and a resolution of 19.21Ωrms at 1MΩ resistance in a conversion time of 5ms, and consumes 152.3μW. It corresponds to state-of-the-art resolution FoM of 14.6pJ/step.
| Original language | English |
|---|---|
| Title of host publication | 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | C60-C61 |
| ISBN (Electronic) | 9784863487185 |
| DOIs | |
| Publication status | Published - 2019 Jun |
| Event | 33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan Duration: 2019 Jun 9 → 2019 Jun 14 |
Publication series
| Name | IEEE Symposium on VLSI Circuits, Digest of Technical Papers |
|---|---|
| Volume | 2019-June |
Conference
| Conference | 33rd Symposium on VLSI Circuits, VLSI Circuits 2019 |
|---|---|
| Country | Japan |
| City | Kyoto |
| Period | 19/6/9 → 19/6/14 |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
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A 0.02mm2 100dB-DR Impedance Monitoring IC with PWM-Dual GRO Architecture. / Han, Hyeonho; Choi, Woojun; Chae, Youngcheol.
2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. p. C60-C61 8778126 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2019-June).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - A 0.02mm2 100dB-DR Impedance Monitoring IC with PWM-Dual GRO Architecture
AU - Han, Hyeonho
AU - Choi, Woojun
AU - Chae, Youngcheol
PY - 2019/6
Y1 - 2019/6
N2 - This paper presents an impedance monitoring IC that achieves small area and wide DR. The stimulated signal is encoded by using pulse width modulation (PWM) and complex impedance can be measured by in- (I) and quadrature- (Q) phase outputs through dual phase demodulation. The two-level I/Q signals drive two gated-ring-oscillator (GRO) based ADCs, thus eliminating the distortion of GROs. Fabricated in 0.11μm CMOS, the prototype IC occupies only 0.02mm2. It achieves a wide DR of 100dB and a resolution of 19.21Ωrms at 1MΩ resistance in a conversion time of 5ms, and consumes 152.3μW. It corresponds to state-of-the-art resolution FoM of 14.6pJ/step.
AB - This paper presents an impedance monitoring IC that achieves small area and wide DR. The stimulated signal is encoded by using pulse width modulation (PWM) and complex impedance can be measured by in- (I) and quadrature- (Q) phase outputs through dual phase demodulation. The two-level I/Q signals drive two gated-ring-oscillator (GRO) based ADCs, thus eliminating the distortion of GROs. Fabricated in 0.11μm CMOS, the prototype IC occupies only 0.02mm2. It achieves a wide DR of 100dB and a resolution of 19.21Ωrms at 1MΩ resistance in a conversion time of 5ms, and consumes 152.3μW. It corresponds to state-of-the-art resolution FoM of 14.6pJ/step.
UR - http://www.scopus.com/inward/record.url?scp=85073911471&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85073911471&partnerID=8YFLogxK
U2 - 10.23919/VLSIC.2019.8778126
DO - 10.23919/VLSIC.2019.8778126
M3 - Conference contribution
AN - SCOPUS:85073911471
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - C60-C61
BT - 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
ER -