A 0.02mm2 100dB-DR Impedance Monitoring IC with PWM-Dual GRO Architecture

Hyeonho Han; Woojun Choi; Youngcheol Chae

doi:10.23919/VLSIC.2019.8778126

A 0.02mm² 100dB-DR Impedance Monitoring IC with PWM-Dual GRO Architecture

Hyeonho Han, Woojun Choi, Youngcheol Chae

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper presents an impedance monitoring IC that achieves small area and wide DR. The stimulated signal is encoded by using pulse width modulation (PWM) and complex impedance can be measured by in- (I) and quadrature- (Q) phase outputs through dual phase demodulation. The two-level I/Q signals drive two gated-ring-oscillator (GRO) based ADCs, thus eliminating the distortion of GROs. Fabricated in 0.11μm CMOS, the prototype IC occupies only 0.02mm². It achieves a wide DR of 100dB and a resolution of 19.21Ω_rms at 1MΩ resistance in a conversion time of 5ms, and consumes 152.3μW. It corresponds to state-of-the-art resolution FoM of 14.6pJ/step.

Original language	English
Title of host publication	2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C60-C61
ISBN (Electronic)	9784863487185
DOIs	https://doi.org/10.23919/VLSIC.2019.8778126
Publication status	Published - 2019 Jun
Event	33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan Duration: 2019 Jun 9 → 2019 Jun 14

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2019-June

Conference

Conference	33rd Symposium on VLSI Circuits, VLSI Circuits 2019
Country	Japan
City	Kyoto
Period	19/6/9 → 19/6/14

Bibliographical note

Funding Information:
This research was supported by SK Hynix and the NRF of Korea (2018M3C7A1024654). Authors would like to thank the Rohde & Schwarz for test instruments.

Publisher Copyright:
© 2019 JSAP.

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

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Han, H., Choi, W., & Chae, Y. (2019). A 0.02mm² 100dB-DR Impedance Monitoring IC with PWM-Dual GRO Architecture. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers (pp. C60-C61). [8778126] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2019-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIC.2019.8778126

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abstract = "This paper presents an impedance monitoring IC that achieves small area and wide DR. The stimulated signal is encoded by using pulse width modulation (PWM) and complex impedance can be measured by in- (I) and quadrature- (Q) phase outputs through dual phase demodulation. The two-level I/Q signals drive two gated-ring-oscillator (GRO) based ADCs, thus eliminating the distortion of GROs. Fabricated in 0.11μm CMOS, the prototype IC occupies only 0.02mm2. It achieves a wide DR of 100dB and a resolution of 19.21Ωrms at 1MΩ resistance in a conversion time of 5ms, and consumes 152.3μW. It corresponds to state-of-the-art resolution FoM of 14.6pJ/step.",

author = "Hyeonho Han and Woojun Choi and Youngcheol Chae",

note = "Funding Information: This research was supported by SK Hynix and the NRF of Korea (2018M3C7A1024654). Authors would like to thank the Rohde & Schwarz for test instruments. Publisher Copyright: {\textcopyright} 2019 JSAP.; 33rd Symposium on VLSI Circuits, VLSI Circuits 2019 ; Conference date: 09-06-2019 Through 14-06-2019",

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Han, H, Choi, W & Chae, Y 2019, A 0.02mm² 100dB-DR Impedance Monitoring IC with PWM-Dual GRO Architecture. in 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers., 8778126, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2019-June, Institute of Electrical and Electronics Engineers Inc., pp. C60-C61, 33rd Symposium on VLSI Circuits, VLSI Circuits 2019, Kyoto, Japan, 19/6/9. https://doi.org/10.23919/VLSIC.2019.8778126

A 0.02mm² 100dB-DR Impedance Monitoring IC with PWM-Dual GRO Architecture. / Han, Hyeonho; Choi, Woojun; Chae, Youngcheol.

2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. p. C60-C61 8778126 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2019-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N1 - Funding Information: This research was supported by SK Hynix and the NRF of Korea (2018M3C7A1024654). Authors would like to thank the Rohde & Schwarz for test instruments. Publisher Copyright: © 2019 JSAP.

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N2 - This paper presents an impedance monitoring IC that achieves small area and wide DR. The stimulated signal is encoded by using pulse width modulation (PWM) and complex impedance can be measured by in- (I) and quadrature- (Q) phase outputs through dual phase demodulation. The two-level I/Q signals drive two gated-ring-oscillator (GRO) based ADCs, thus eliminating the distortion of GROs. Fabricated in 0.11μm CMOS, the prototype IC occupies only 0.02mm2. It achieves a wide DR of 100dB and a resolution of 19.21Ωrms at 1MΩ resistance in a conversion time of 5ms, and consumes 152.3μW. It corresponds to state-of-the-art resolution FoM of 14.6pJ/step.

AB - This paper presents an impedance monitoring IC that achieves small area and wide DR. The stimulated signal is encoded by using pulse width modulation (PWM) and complex impedance can be measured by in- (I) and quadrature- (Q) phase outputs through dual phase demodulation. The two-level I/Q signals drive two gated-ring-oscillator (GRO) based ADCs, thus eliminating the distortion of GROs. Fabricated in 0.11μm CMOS, the prototype IC occupies only 0.02mm2. It achieves a wide DR of 100dB and a resolution of 19.21Ωrms at 1MΩ resistance in a conversion time of 5ms, and consumes 152.3μW. It corresponds to state-of-the-art resolution FoM of 14.6pJ/step.

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Han H, Choi W, Chae Y. A 0.02mm² 100dB-DR Impedance Monitoring IC with PWM-Dual GRO Architecture. In 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2019. p. C60-C61. 8778126. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.23919/VLSIC.2019.8778126