A 0.033-mm221.5-AF Resolution Continuous-Time Delta-Sigma Capacitance-To-Digital Converter with Parasitic Capacitance Immunity up to 480pF

Hyeyeon Lee, Changuk Lee, Jae Youl Lee, Yoon Kyung Choi, Youngcheol Chae

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)


Smart devices incorporating 3D hover or fingerprint sensor require a high-resolution capacitance-To-digital converter (CDC) to detect very small changes in capacitance of only tens of aF [1]. Although the switched-capacitor (SC) delta-sigma (ΔΣ) CDCs have accomplished high resolution [2], [3], the SC ΔΣ CDCs suffer from sampling noise penalty and are prone to an input parasitic capacitor (CP). In addition to the resolution, the CDCs in the systems are designed for low power consumption and small areas, considering integration in mobile devices. The current conveyor front-end is proposed in [1] and effectively isolates the CP from the following ADC, resulting in high energy efficiency. However, the work in [1] achieved a limited CP immunity (only 30pF) and is sensitive to high-frequency interference due to the limitation of SC ΔΣ CDCs. In this work, a continuous-Time (CT) ΔΣ CDC, which consists of a class-AB current conveyor and a CT ΔΣ ADC, is proposed. Implemented in a small area of 0.033mm2, it achieves 21.5-pF resolution with a high CP immunity of 480pF and a tolerance to high-frequency interference.

Original languageEnglish
Title of host publicationProceedings - A-SSCC 2021
Subtitle of host publicationIEEE Asian Solid-State Circuits Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665443500
Publication statusPublished - 2021
Event2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021 - Busan, Korea, Republic of
Duration: 2021 Nov 72021 Nov 10

Publication series

NameProceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference


Conference2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021
Country/TerritoryKorea, Republic of

Bibliographical note

Funding Information:
The prototype CDC fabricated in a 0.11-μm CMOS process occupies only 0.033mm2 (Fig. 7). The total power consumption is only 120μW at a supply voltage of 1.5V. Fig.4 shows the measured output PSD with and without a large CP (=480pF). It shows the 2nd-order noise shaping and the thermal noise level of -100dB. Even though two output PSDs are captured with the same CIN=0.2pF, the result with the large CP shows a slight noise increase. The capacitance resolution across the OSR is also shown. As the OSR increases, the capacitance resolution is improved. At the OSR of 600, the capacitance resolution with and without CP is measured to be 119.4aF and 21.5aF, respectively. The capacitance resolution is also measured with the CIN of 0.2pF to 1.5pF, and it varies from 21.5aF to 59aF without CP. With the large CP, this work can still achieve the capacitance resolution of 119aF to 143aF. Fig. 5 shows the noise measurement setup for evaluating interference immunity, the results of which are very important for 3D hover or fingerprint sensors. The fDRV and fS are produced by the clock generator and the 10-VPP sinusoidal noise is injected through the coupling capacitor (CC) of 1pF. With CIN of 0.5, 1, and 1.5pF, the averaged value of measured capacitance resolution for the in-band frequencies is 30.5, 54.6, and 63.7aF, respectively. With the same CIN in presence of the large CP, the averaged value of measured capacitance resolution is 128.9, 142.8, and 149.1aF, respectively. Compared to [1], this result shows significant improvements mainly due to the anti-aliasing property of the CT-CDC. Fig. 6 shows the performance summary and comparison with previous state-of-the-art works. This work achieves the smallest area. It attains the smallest capacitance resolution of 21.5aF and the competitive FoM of 7.14pJ/step. It also shows the best CP immunity up to 480pF, more than 16× improvements over previous benchmarks [1,4]. Acknowledgement: This work was supported by Samsung Electronics and in part by NRF (National Research Foundation of Korea) Grant funded by the Korean Government (NRF-2017-Global Ph.D. Fellowship Program). References: [1] H. Hwang, et al., “A 1.8-V 6.9-mW 120-fps 50-Channel Capacitive Touch Readout With Current Conveyor AFE and Current-Driven ΔΣ ADC,” IEEE JSSC 2018:204-218. [2] R. Yang, et al., "A Precision Capacitance-to-Digital Converter With 16.7-bit ENOB and 7.5-ppm/°C Thermal Drift," IEEE JSSC 2017:3018-3031. [3] N. Narasimman, et al., "A 1.2 V, 0.84 pJ/Conv.-Step Ultra-low Power Capacitance to Digital Converter for Microphone based Auscultation," CICC 2017:1-4. [4] A. K. George, et al., "A 114-aFrms-Resolution 46-nF/10-MΩ-Range Digital-Intensive Reconfigurable RC-to-Digital Converter with Parasitic-Insensitive Femto-Farad Baseline Sensing,” IEEE VLSI 2018: 157-158. [5] M. Jang, et al., "Analysis and Design of Low-Power Continuous-Time Delta-Sigma Modulator Using Negative-R Assisted Integrator," IEEE JSSC 2019:277-287.

Publisher Copyright:
© 2021 IEEE.

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Signal Processing
  • Electrical and Electronic Engineering


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