TY - JOUR
T1 - A 0.033-mm221.5-aF to 114.9-aF Resolution Continuous-Time Δ Σ Capacitance-to-Digital Converter Achieving Parasitic Capacitance Immunity Up to 480 pF
AU - Lee, Hyeyeon
AU - Lee, Changuk
AU - Lee, Inhee
AU - Chae, Youngcheol
N1 - Publisher Copyright:
© 1966-2012 IEEE.
PY - 2022/10/1
Y1 - 2022/10/1
N2 - This article presents a continuous-time (CT) delta-sigma ( Δ Σ ) capacitance-to-digital converter (CDC) intended for use in applications with high capacitance resolution (tens of aF), and a large parasitic capacitance CP (> 400 pF). It consists of a current conveyor (CC) front-end and a CT Δ Σ modulator. The CC-based front-end isolates CP from the first integrator of the modulator, and the CC's output current is directly coupled to the CT Δ Σ modulator. The CC uses a class-AB configuration, which enables to maintain energy efficiency and its capacitance resolution even with CP. The proposed CDC is fabricated in a 110-nm CMOS process and occupies only 0.033 mm2. It achieves a capacitance resolution of 21.5-59 aF with an input range of 0.2-1.5 pF. This corresponds to an effective resolution of 14.3 bits in a conversion time of 1.2 ms, while drawing only 120 μW from a 1.5-V supply. It also achieves a capacitance resolution of 119.4 aF with CP of 480 pF, offering robust capacitance resolution with external noise interference (10 VPP).
AB - This article presents a continuous-time (CT) delta-sigma ( Δ Σ ) capacitance-to-digital converter (CDC) intended for use in applications with high capacitance resolution (tens of aF), and a large parasitic capacitance CP (> 400 pF). It consists of a current conveyor (CC) front-end and a CT Δ Σ modulator. The CC-based front-end isolates CP from the first integrator of the modulator, and the CC's output current is directly coupled to the CT Δ Σ modulator. The CC uses a class-AB configuration, which enables to maintain energy efficiency and its capacitance resolution even with CP. The proposed CDC is fabricated in a 110-nm CMOS process and occupies only 0.033 mm2. It achieves a capacitance resolution of 21.5-59 aF with an input range of 0.2-1.5 pF. This corresponds to an effective resolution of 14.3 bits in a conversion time of 1.2 ms, while drawing only 120 μW from a 1.5-V supply. It also achieves a capacitance resolution of 119.4 aF with CP of 480 pF, offering robust capacitance resolution with external noise interference (10 VPP).
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U2 - 10.1109/JSSC.2022.3184531
DO - 10.1109/JSSC.2022.3184531
M3 - Article
AN - SCOPUS:85133695796
SN - 0018-9200
VL - 57
SP - 3048
EP - 3057
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 10
ER -