A 0.1-pj/b/db 1.62-To-10.8-gb/s video interface receiver with jointly adaptive ctle and dfe using biased data-level reference

Jinhyung Lee, Kwangho Lee, Hyojun Kim, Byungmin Kim, Kwanseo Park, Deog Kyoon Jeong

Research output: Contribution to journalArticlepeer-review

12 Citations (Scopus)

Abstract

In this article, a 1.62-To-10.8-Gb/s video interface receiver with jointly adaptive equalization is presented. Sign-sign least-mean-squares (SSLMS) algorithm is applied to adaptation for not only a decision feedback equalizer (DFE) but also a continuous-Time linear equalizer (CTLE) to unify the adaptation methods. This approach facilitates concurrent adaptation that results in short adaptation time and also reduces the extra hardware and power consumption. An average value of fourth-and fifth-post-cursors is used as an indicator for CTLE adaptation, and the validity is substantiated by numerical analysis and simulation. Furthermore, the concept of a biased data-level reference (dLev) is proposed and analyzed to alleviate insufficient adaptation of the SSLMS algorithm in the presence of pre-cursor inter-symbol interference (ISI). The proposed dLev is acquired by simply adjusting up and down ratios of the dLev update equation. The prototype test chip is implemented in 65-nm CMOS technology and occupies an active area of 0.174 mm2. The proposed adaptive equalizers compensate for the channel loss of up to 34 dB at 10.8 Gb/s. Total power consumption of the receiver is 37.2 mW at 10.8 Gb/s, and the figure of merit (energy efficiency per channel loss at Nyquist frequency) of 0.1 pJ/b/dB is achieved.

Original languageEnglish
Article number9082099
Pages (from-to)2186-2195
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume55
Issue number8
DOIs
Publication statusPublished - 2020 Aug

Bibliographical note

Publisher Copyright:
© 1966-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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