Abstract
A new compact line equalizer is proposed for backplane serial link applications. The equalizer has two control blocks. The feed-forward swing control block determines the optimal low frequency level and the feedback control block detects signal shapes and decides the high-frequency boosting level of the equalizer. Successful equalization is demonstrated over a 1.5 m long PCB trace at 3.125-Gb/s by the circuit realized with 0.18 μm CMOS process. The circuit occupies only 0.16 mm2 and consumes 20 mW with 1.8 V supply.
| Original language | English |
|---|---|
| Pages (from-to) | 1454-1459 |
| Number of pages | 6 |
| Journal | IEICE Transactions on Electronics |
| Volume | E89-C |
| Issue number | 10 |
| DOIs | |
| Publication status | Published - 2006 Oct |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
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A 0.18 μm CMOS 3.125-Gb/s digitally controlled adaptive line equalizer with feed-forward swing control for backplane serial link. / Lee, Ki Hyuk; Lee, Jae Wook; Choi, Woo Young.
In: IEICE Transactions on Electronics, Vol. E89-C, No. 10, 10.2006, p. 1454-1459.Research output: Contribution to journal › Article
TY - JOUR
T1 - A 0.18 μm CMOS 3.125-Gb/s digitally controlled adaptive line equalizer with feed-forward swing control for backplane serial link
AU - Lee, Ki Hyuk
AU - Lee, Jae Wook
AU - Choi, Woo Young
PY - 2006/10
Y1 - 2006/10
N2 - A new compact line equalizer is proposed for backplane serial link applications. The equalizer has two control blocks. The feed-forward swing control block determines the optimal low frequency level and the feedback control block detects signal shapes and decides the high-frequency boosting level of the equalizer. Successful equalization is demonstrated over a 1.5 m long PCB trace at 3.125-Gb/s by the circuit realized with 0.18 μm CMOS process. The circuit occupies only 0.16 mm2 and consumes 20 mW with 1.8 V supply.
AB - A new compact line equalizer is proposed for backplane serial link applications. The equalizer has two control blocks. The feed-forward swing control block determines the optimal low frequency level and the feedback control block detects signal shapes and decides the high-frequency boosting level of the equalizer. Successful equalization is demonstrated over a 1.5 m long PCB trace at 3.125-Gb/s by the circuit realized with 0.18 μm CMOS process. The circuit occupies only 0.16 mm2 and consumes 20 mW with 1.8 V supply.
UR - http://www.scopus.com/inward/record.url?scp=33750069469&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33750069469&partnerID=8YFLogxK
U2 - 10.1093/ietele/e89-c.10.1454
DO - 10.1093/ietele/e89-c.10.1454
M3 - Article
AN - SCOPUS:33750069469
VL - E89-C
SP - 1454
EP - 1459
JO - IEICE Transactions on Electronics
JF - IEICE Transactions on Electronics
SN - 0916-8524
IS - 10
ER -