A new compact line equalizer is proposed for backplane serial link applications. The equalizer has two control blocks. The feed-forward swing control block determines the optimal low frequency level and the feedback control block detects signal shapes and decides the high-frequency boosting level of the equalizer. Successful equalization is demonstrated over a 1.5 m long PCB trace at 3.125-Gb/s by the circuit realized with 0.18 μm CMOS process. The circuit occupies only 0.16 mm2 and consumes 20 mW with 1.8 V supply.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering