A 0.36 pJ/bit, 0.025 mm2 12.5 Gb/s Forwarded-Clock Receiver with a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology

Woorham Bae, Gyu Seob Jeong, Kwanseo Park, Sung Yong Cho, Yoonsoo Kim, Deog Kyoon Jeong

Research output: Contribution to journalArticlepeer-review

18 Citations (Scopus)

Abstract

This paper describes a power and area-efficient forwarded-clock (FC) receiver and includes an analysis of the jitter tolerance of the FC receiver. In the proposed design, jitter tolerance is maximized according to the analysis by employing a delay-locked loop (DLL) based de-skewing. A sample-swapping bang-bang phase-detector (SS-BBPD) eliminates the stuck locking caused by the finite delay range of the voltage-controlled delay line (VCDL), and also reduces the required delay range of the VCDL by half. The proposed FC receiver is fabricated in 65-nm CMOS technology and occupies an active area of 0.025 mm2. At a data rate of 12.5 Gb/s, the proposed FC receiver exhibits an energy efficiency of 0.36 pJ/bit, and tolerates 1.4-\text{UI}-{\mathrm{pp}} sinusoidal jitter of 300 MHz.

Original languageEnglish
Article number7536167
Pages (from-to)1393-1403
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume63
Issue number9
DOIs
Publication statusPublished - 2016 Sep

Bibliographical note

Funding Information:
This work was supported by the Center for Integrated Smart Sensors funded by the Ministry of Science, ICT & Future Planning as a Global Frontier Project (CISS-2012M3A6A6054191).

Publisher Copyright:
© 2004-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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