A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line

Woorham Bae, Gyu Seob Jeong, Kwanseo Park, Sung Yong Cho, Yoonsoo Kim, Deog Kyoon Jeong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

A 12.5Gb/s forwarded clock receiver based on a DLL with a bang-bang PD is presented. The stuck locking is detected and averted by swapping edge and data samples at the output of the PD. Moreover, required delay range of the VCDL is reduced by half with the proposed sample swapping scheme. The prototype chip exhibits the power efficiency of 0.36pJ/bit and occupies 0.025mm2. Due to the wide jitter tracking bandwidth of DLL and the inherent jitter correlation between data and forwarded clock, the proposed receiver exhibits outstanding jitter tolerance whose corner frequency is higher than 300 MHz.

Original languageEnglish
Title of host publicationESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference
EditorsPietro Andreani, Andrea Bevilacqua, Gaudenzio Meneghesso
PublisherIEEE Computer Society
Pages447-450
Number of pages4
ISBN (Electronic)9781479956944
DOIs
Publication statusPublished - 2014 Oct 31
Event40th European Solid-State Circuit Conference, ESSCIRC 2014 - Venezia Lido, Italy
Duration: 2014 Sep 222014 Sep 26

Publication series

NameEuropean Solid-State Circuits Conference
ISSN (Print)1930-8833

Conference

Conference40th European Solid-State Circuit Conference, ESSCIRC 2014
Country/TerritoryItaly
CityVenezia Lido
Period14/9/2214/9/26

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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