A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line

Woorham Bae, Gyu Seob Jeong, Kwanseo Park, Sung Yong Cho, Yoonsoo Kim, Deog Kyoon Jeong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

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Engineering & Materials Science