A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation

Joung Wook Moon, Sung Geun Kim, Dae Hyun Kwon, Woo Young Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

We present a 500-MHz, ultra-low-power phase-locked loop (PLL) realized with the near-threshold supply voltage of 0.4 V in 65-nm CMOS technology. Our PLL employs a new charge pump (CP) circuit structure that can greatly reduce CP up/down current mismatch and their variation with voltage-controlled oscillator (VCO) control voltages. The PLL consumes only 127.8 μW, which corresponds to power efficiency of 0.256 mW/GHz.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479932863
DOIs
Publication statusPublished - 2014 Jan 1
Event36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014 - San Jose, United States
Duration: 2014 Sep 152014 Sep 17

Other

Other36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014
CountryUnited States
CitySan Jose
Period14/9/1514/9/17

Fingerprint

Phase locked loops
Threshold voltage
Charge pump circuits
Variable frequency oscillators
Voltage control
Pumps
Electric potential

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Moon, J. W., Kim, S. G., Kwon, D. H., & Choi, W. Y. (2014). A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014 [6946100] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2014.6946100
Moon, Joung Wook ; Kim, Sung Geun ; Kwon, Dae Hyun ; Choi, Woo Young. / A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation. Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc., 2014.
@inproceedings{cae9831138ef414b8a1523b20a2ebe24,
title = "A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation",
abstract = "We present a 500-MHz, ultra-low-power phase-locked loop (PLL) realized with the near-threshold supply voltage of 0.4 V in 65-nm CMOS technology. Our PLL employs a new charge pump (CP) circuit structure that can greatly reduce CP up/down current mismatch and their variation with voltage-controlled oscillator (VCO) control voltages. The PLL consumes only 127.8 μW, which corresponds to power efficiency of 0.256 mW/GHz.",
author = "Moon, {Joung Wook} and Kim, {Sung Geun} and Kwon, {Dae Hyun} and Choi, {Woo Young}",
year = "2014",
month = "1",
day = "1",
doi = "10.1109/CICC.2014.6946100",
language = "English",
booktitle = "Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",

}

Moon, JW, Kim, SG, Kwon, DH & Choi, WY 2014, A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation. in Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014., 6946100, Institute of Electrical and Electronics Engineers Inc., 36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014, San Jose, United States, 14/9/15. https://doi.org/10.1109/CICC.2014.6946100

A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation. / Moon, Joung Wook; Kim, Sung Geun; Kwon, Dae Hyun; Choi, Woo Young.

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 6946100.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation

AU - Moon, Joung Wook

AU - Kim, Sung Geun

AU - Kwon, Dae Hyun

AU - Choi, Woo Young

PY - 2014/1/1

Y1 - 2014/1/1

N2 - We present a 500-MHz, ultra-low-power phase-locked loop (PLL) realized with the near-threshold supply voltage of 0.4 V in 65-nm CMOS technology. Our PLL employs a new charge pump (CP) circuit structure that can greatly reduce CP up/down current mismatch and their variation with voltage-controlled oscillator (VCO) control voltages. The PLL consumes only 127.8 μW, which corresponds to power efficiency of 0.256 mW/GHz.

AB - We present a 500-MHz, ultra-low-power phase-locked loop (PLL) realized with the near-threshold supply voltage of 0.4 V in 65-nm CMOS technology. Our PLL employs a new charge pump (CP) circuit structure that can greatly reduce CP up/down current mismatch and their variation with voltage-controlled oscillator (VCO) control voltages. The PLL consumes only 127.8 μW, which corresponds to power efficiency of 0.256 mW/GHz.

UR - http://www.scopus.com/inward/record.url?scp=84928152160&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84928152160&partnerID=8YFLogxK

U2 - 10.1109/CICC.2014.6946100

DO - 10.1109/CICC.2014.6946100

M3 - Conference contribution

BT - Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Moon JW, Kim SG, Kwon DH, Choi WY. A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 6946100 https://doi.org/10.1109/CICC.2014.6946100