A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation

Joung Wook Moon, Sung Geun Kim, Dae Hyun Kwon, Woo Young Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

We present a 500-MHz, ultra-low-power phase-locked loop (PLL) realized with the near-threshold supply voltage of 0.4 V in 65-nm CMOS technology. Our PLL employs a new charge pump (CP) circuit structure that can greatly reduce CP up/down current mismatch and their variation with voltage-controlled oscillator (VCO) control voltages. The PLL consumes only 127.8 μW, which corresponds to power efficiency of 0.256 mW/GHz.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479932863
DOIs
Publication statusPublished - 2014 Nov 4
Event36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014 - San Jose, United States
Duration: 2014 Sep 152014 Sep 17

Publication series

NameProceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014

Other

Other36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014
CountryUnited States
CitySan Jose
Period14/9/1514/9/17

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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