A 0.4-V, 90 ∼ 350-MHz PLL with an active loop-filter charge pump

Joung Wook Moon, Kwang Chun Choi, Woo-Young Choi

Research output: Contribution to journalArticle

23 Citations (Scopus)

Abstract

A 0.4-V phase-locked loop (PLL) that has much improved power efficiency is realized in standard 65-nm CMOS. The PLL employs a novel ultralow-voltage charge pump that compensates current mismatch with an active loop filter and produces significantly reduced reference spurs. Its voltage-controlled oscillator (VCO) is designed with the body-bias technique and includes an automatic frequency calibration circuit that provides low VCO gain and wide tuning range. The PLL output frequency can be tuned from 90 to 350 MHz. At 350-MHz output, the PLL consumes 109 μW, which corresponds to the power efficiency of 0.31 mW/GHz.

Original languageEnglish
Article number6805603
Pages (from-to)319-323
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume61
Issue number5
DOIs
Publication statusPublished - 2014 Jan 1

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Phase locked loops
Pumps
Variable frequency oscillators
Tuning
Calibration
Networks (circuits)
Electric potential

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

@article{f107090bc84648fd8d413a2ebdd7e328,
title = "A 0.4-V, 90 ∼ 350-MHz PLL with an active loop-filter charge pump",
abstract = "A 0.4-V phase-locked loop (PLL) that has much improved power efficiency is realized in standard 65-nm CMOS. The PLL employs a novel ultralow-voltage charge pump that compensates current mismatch with an active loop filter and produces significantly reduced reference spurs. Its voltage-controlled oscillator (VCO) is designed with the body-bias technique and includes an automatic frequency calibration circuit that provides low VCO gain and wide tuning range. The PLL output frequency can be tuned from 90 to 350 MHz. At 350-MHz output, the PLL consumes 109 μW, which corresponds to the power efficiency of 0.31 mW/GHz.",
author = "Moon, {Joung Wook} and Choi, {Kwang Chun} and Woo-Young Choi",
year = "2014",
month = "1",
day = "1",
doi = "10.1109/TCSII.2014.2312800",
language = "English",
volume = "61",
pages = "319--323",
journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",
issn = "1549-7747",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "5",

}

A 0.4-V, 90 ∼ 350-MHz PLL with an active loop-filter charge pump. / Moon, Joung Wook; Choi, Kwang Chun; Choi, Woo-Young.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 61, No. 5, 6805603, 01.01.2014, p. 319-323.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A 0.4-V, 90 ∼ 350-MHz PLL with an active loop-filter charge pump

AU - Moon, Joung Wook

AU - Choi, Kwang Chun

AU - Choi, Woo-Young

PY - 2014/1/1

Y1 - 2014/1/1

N2 - A 0.4-V phase-locked loop (PLL) that has much improved power efficiency is realized in standard 65-nm CMOS. The PLL employs a novel ultralow-voltage charge pump that compensates current mismatch with an active loop filter and produces significantly reduced reference spurs. Its voltage-controlled oscillator (VCO) is designed with the body-bias technique and includes an automatic frequency calibration circuit that provides low VCO gain and wide tuning range. The PLL output frequency can be tuned from 90 to 350 MHz. At 350-MHz output, the PLL consumes 109 μW, which corresponds to the power efficiency of 0.31 mW/GHz.

AB - A 0.4-V phase-locked loop (PLL) that has much improved power efficiency is realized in standard 65-nm CMOS. The PLL employs a novel ultralow-voltage charge pump that compensates current mismatch with an active loop filter and produces significantly reduced reference spurs. Its voltage-controlled oscillator (VCO) is designed with the body-bias technique and includes an automatic frequency calibration circuit that provides low VCO gain and wide tuning range. The PLL output frequency can be tuned from 90 to 350 MHz. At 350-MHz output, the PLL consumes 109 μW, which corresponds to the power efficiency of 0.31 mW/GHz.

UR - http://www.scopus.com/inward/record.url?scp=84901355973&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84901355973&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2014.2312800

DO - 10.1109/TCSII.2014.2312800

M3 - Article

VL - 61

SP - 319

EP - 323

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

SN - 1549-7747

IS - 5

M1 - 6805603

ER -