Abstract
A 0.4-V phase-locked loop (PLL) that has much improved power efficiency is realized in standard 65-nm CMOS. The PLL employs a novel ultralow-voltage charge pump that compensates current mismatch with an active loop filter and produces significantly reduced reference spurs. Its voltage-controlled oscillator (VCO) is designed with the body-bias technique and includes an automatic frequency calibration circuit that provides low VCO gain and wide tuning range. The PLL output frequency can be tuned from 90 to 350 MHz. At 350-MHz output, the PLL consumes 109 μW, which corresponds to the power efficiency of 0.31 mW/GHz.
| Original language | English |
|---|---|
| Article number | 6805603 |
| Pages (from-to) | 319-323 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 61 |
| Issue number | 5 |
| DOIs | |
| Publication status | Published - 2014 Jan 1 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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A 0.4-V, 90 ∼ 350-MHz PLL with an active loop-filter charge pump. / Moon, Joung Wook; Choi, Kwang Chun; Choi, Woo-Young.
In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 61, No. 5, 6805603, 01.01.2014, p. 319-323.Research output: Contribution to journal › Article
TY - JOUR
T1 - A 0.4-V, 90 ∼ 350-MHz PLL with an active loop-filter charge pump
AU - Moon, Joung Wook
AU - Choi, Kwang Chun
AU - Choi, Woo-Young
PY - 2014/1/1
Y1 - 2014/1/1
N2 - A 0.4-V phase-locked loop (PLL) that has much improved power efficiency is realized in standard 65-nm CMOS. The PLL employs a novel ultralow-voltage charge pump that compensates current mismatch with an active loop filter and produces significantly reduced reference spurs. Its voltage-controlled oscillator (VCO) is designed with the body-bias technique and includes an automatic frequency calibration circuit that provides low VCO gain and wide tuning range. The PLL output frequency can be tuned from 90 to 350 MHz. At 350-MHz output, the PLL consumes 109 μW, which corresponds to the power efficiency of 0.31 mW/GHz.
AB - A 0.4-V phase-locked loop (PLL) that has much improved power efficiency is realized in standard 65-nm CMOS. The PLL employs a novel ultralow-voltage charge pump that compensates current mismatch with an active loop filter and produces significantly reduced reference spurs. Its voltage-controlled oscillator (VCO) is designed with the body-bias technique and includes an automatic frequency calibration circuit that provides low VCO gain and wide tuning range. The PLL output frequency can be tuned from 90 to 350 MHz. At 350-MHz output, the PLL consumes 109 μW, which corresponds to the power efficiency of 0.31 mW/GHz.
UR - http://www.scopus.com/inward/record.url?scp=84901355973&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84901355973&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2014.2312800
DO - 10.1109/TCSII.2014.2312800
M3 - Article
VL - 61
SP - 319
EP - 323
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
SN - 1549-7747
IS - 5
M1 - 6805603
ER -