A 0.4-V, 90 ∼ 350-MHz PLL with an active loop-filter charge pump

Joung Wook Moon; Kwang Chun Choi; Woo Young Choi

doi:10.1109/TCSII.2014.2312800

A 0.4-V, 90 ∼ 350-MHz PLL with an active loop-filter charge pump

Joung Wook Moon, Kwang Chun Choi, Woo Young Choi

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

31 Citations (Scopus)

Abstract

A 0.4-V phase-locked loop (PLL) that has much improved power efficiency is realized in standard 65-nm CMOS. The PLL employs a novel ultralow-voltage charge pump that compensates current mismatch with an active loop filter and produces significantly reduced reference spurs. Its voltage-controlled oscillator (VCO) is designed with the body-bias technique and includes an automatic frequency calibration circuit that provides low VCO gain and wide tuning range. The PLL output frequency can be tuned from 90 to 350 MHz. At 350-MHz output, the PLL consumes 109 μW, which corresponds to the power efficiency of 0.31 mW/GHz.

Original language	English
Article number	6805603
Pages (from-to)	319-323
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	61
Issue number	5
DOIs	https://doi.org/10.1109/TCSII.2014.2312800
Publication status	Published - 2014 May

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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abstract = "A 0.4-V phase-locked loop (PLL) that has much improved power efficiency is realized in standard 65-nm CMOS. The PLL employs a novel ultralow-voltage charge pump that compensates current mismatch with an active loop filter and produces significantly reduced reference spurs. Its voltage-controlled oscillator (VCO) is designed with the body-bias technique and includes an automatic frequency calibration circuit that provides low VCO gain and wide tuning range. The PLL output frequency can be tuned from 90 to 350 MHz. At 350-MHz output, the PLL consumes 109 μW, which corresponds to the power efficiency of 0.31 mW/GHz.",

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AB - A 0.4-V phase-locked loop (PLL) that has much improved power efficiency is realized in standard 65-nm CMOS. The PLL employs a novel ultralow-voltage charge pump that compensates current mismatch with an active loop filter and produces significantly reduced reference spurs. Its voltage-controlled oscillator (VCO) is designed with the body-bias technique and includes an automatic frequency calibration circuit that provides low VCO gain and wide tuning range. The PLL output frequency can be tuned from 90 to 350 MHz. At 350-MHz output, the PLL consumes 109 μW, which corresponds to the power efficiency of 0.31 mW/GHz.

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