A 0.6-V +4 dBm IIP3 LC folded cascode CMOS LNA with gm linearization

Yeo Myung Kim, Honggul Han, tae wook Kim

Research output: Contribution to journalArticle

21 Citations (Scopus)

Abstract

This brief presents the design guidelines of LNAs under low-supply-voltage condition with respect to linearity and demonstrates an LNA that has excellent performance even with an extremely low supply voltage. Under a low supply voltage, the drain conductance nonlinearity, which can be ignored in a high supply voltage, is important, as well as the transconductance nonlinearity. Therefore, this brief linearizes transconductance using the multiple-gated transistor (MGTR) technique and tries to obtain high drain conductance linearity with the LC folded cascode configuration. The proposed 900-MHz LNA is designed with a 130-nm CMOS process. The measurement results show a gain of 15.4 dB, a noise figure of 1.74 dB, and an IIP3 of 4.09 dBm, which is the result of the 4.94-dB improvement over a conventional LC folded cascode LNA at 5.16-mW power consumption with a 0.6-V supply voltage.

Original languageEnglish
Article number6475990
Pages (from-to)122-126
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume60
Issue number3
DOIs
Publication statusPublished - 2013 Mar 13

Fingerprint

Linearization
Electric potential
Transconductance
Noise figure
Transistors
Electric power utilization

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

@article{7cd65249e7a5452e8a7ed7516288332c,
title = "A 0.6-V +4 dBm IIP3 LC folded cascode CMOS LNA with gm linearization",
abstract = "This brief presents the design guidelines of LNAs under low-supply-voltage condition with respect to linearity and demonstrates an LNA that has excellent performance even with an extremely low supply voltage. Under a low supply voltage, the drain conductance nonlinearity, which can be ignored in a high supply voltage, is important, as well as the transconductance nonlinearity. Therefore, this brief linearizes transconductance using the multiple-gated transistor (MGTR) technique and tries to obtain high drain conductance linearity with the LC folded cascode configuration. The proposed 900-MHz LNA is designed with a 130-nm CMOS process. The measurement results show a gain of 15.4 dB, a noise figure of 1.74 dB, and an IIP3 of 4.09 dBm, which is the result of the 4.94-dB improvement over a conventional LC folded cascode LNA at 5.16-mW power consumption with a 0.6-V supply voltage.",
author = "Kim, {Yeo Myung} and Honggul Han and Kim, {tae wook}",
year = "2013",
month = "3",
day = "13",
doi = "10.1109/TCSII.2013.2240811",
language = "English",
volume = "60",
pages = "122--126",
journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",
issn = "1549-7747",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "3",

}

A 0.6-V +4 dBm IIP3 LC folded cascode CMOS LNA with gm linearization. / Kim, Yeo Myung; Han, Honggul; Kim, tae wook.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 60, No. 3, 6475990, 13.03.2013, p. 122-126.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A 0.6-V +4 dBm IIP3 LC folded cascode CMOS LNA with gm linearization

AU - Kim, Yeo Myung

AU - Han, Honggul

AU - Kim, tae wook

PY - 2013/3/13

Y1 - 2013/3/13

N2 - This brief presents the design guidelines of LNAs under low-supply-voltage condition with respect to linearity and demonstrates an LNA that has excellent performance even with an extremely low supply voltage. Under a low supply voltage, the drain conductance nonlinearity, which can be ignored in a high supply voltage, is important, as well as the transconductance nonlinearity. Therefore, this brief linearizes transconductance using the multiple-gated transistor (MGTR) technique and tries to obtain high drain conductance linearity with the LC folded cascode configuration. The proposed 900-MHz LNA is designed with a 130-nm CMOS process. The measurement results show a gain of 15.4 dB, a noise figure of 1.74 dB, and an IIP3 of 4.09 dBm, which is the result of the 4.94-dB improvement over a conventional LC folded cascode LNA at 5.16-mW power consumption with a 0.6-V supply voltage.

AB - This brief presents the design guidelines of LNAs under low-supply-voltage condition with respect to linearity and demonstrates an LNA that has excellent performance even with an extremely low supply voltage. Under a low supply voltage, the drain conductance nonlinearity, which can be ignored in a high supply voltage, is important, as well as the transconductance nonlinearity. Therefore, this brief linearizes transconductance using the multiple-gated transistor (MGTR) technique and tries to obtain high drain conductance linearity with the LC folded cascode configuration. The proposed 900-MHz LNA is designed with a 130-nm CMOS process. The measurement results show a gain of 15.4 dB, a noise figure of 1.74 dB, and an IIP3 of 4.09 dBm, which is the result of the 4.94-dB improvement over a conventional LC folded cascode LNA at 5.16-mW power consumption with a 0.6-V supply voltage.

UR - http://www.scopus.com/inward/record.url?scp=84875367174&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84875367174&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2013.2240811

DO - 10.1109/TCSII.2013.2240811

M3 - Article

VL - 60

SP - 122

EP - 126

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

SN - 1549-7747

IS - 3

M1 - 6475990

ER -