A 0.6V 86.5dB-DR 40kHz-BW Inverter-Based Continuous-Time Delta-Sigma Modulator with PVT-Robust Body-Biasing Technique

Sangwoo Lee; Sungsik Park; Yunhong Kim; Youngcheol Chae

doi:10.23919/VLSICircuits52068.2021.9492519

A 0.6V 86.5dB-DR 40kHz-BW Inverter-Based Continuous-Time Delta-Sigma Modulator with PVT-Robust Body-Biasing Technique

Sangwoo Lee, Sungsik Park, Yunhong Kim, Youngcheol Chae

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper presents a body-biasing technique for an energy-efficient inverter-based integrator that significantly improves the PVT robustness of the integrators in sub-1V continuous-time delta-sigma modulators (CTDSMs). A prototype CTDSM with the body-biasing technique is implemented in a 28 nm CMOS process and achieves 83 dB SNDR, 84 dB SNR, and 86.5 dB DR in a 40-kHz bandwidth, while consuming only 33.6 μW from a 0.6 V supply. It achieves a Schreier FoM of 177.3 dB.

Original language	English
Title of host publication	2021 Symposium on VLSI Circuits, VLSI Circuits 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9784863487796
DOIs	https://doi.org/10.23919/VLSICircuits52068.2021.9492519
Publication status	Published - 2021 Jun 13
Event	35th Symposium on VLSI Circuits, VLSI Circuits 2021 - Virutal, Online Duration: 2021 Jun 13 → 2021 Jun 19

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2021-June

Conference

Conference	35th Symposium on VLSI Circuits, VLSI Circuits 2021
City	Virutal, Online
Period	21/6/13 → 21/6/19

Bibliographical note

Funding Information:
This work is funded by Samsung Electronics (2020-11-1553).

Publisher Copyright:
© 2021 JSAP.

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.23919/VLSICircuits52068.2021.9492519

Cite this

Lee, S., Park, S., Kim, Y., & Chae, Y. (2021). A 0.6V 86.5dB-DR 40kHz-BW Inverter-Based Continuous-Time Delta-Sigma Modulator with PVT-Robust Body-Biasing Technique. In 2021 Symposium on VLSI Circuits, VLSI Circuits 2021 [9492519] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2021-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSICircuits52068.2021.9492519

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abstract = "This paper presents a body-biasing technique for an energy-efficient inverter-based integrator that significantly improves the PVT robustness of the integrators in sub-1V continuous-time delta-sigma modulators (CTDSMs). A prototype CTDSM with the body-biasing technique is implemented in a 28 nm CMOS process and achieves 83 dB SNDR, 84 dB SNR, and 86.5 dB DR in a 40-kHz bandwidth, while consuming only 33.6 μW from a 0.6 V supply. It achieves a Schreier FoM of 177.3 dB.",

author = "Sangwoo Lee and Sungsik Park and Yunhong Kim and Youngcheol Chae",

note = "Funding Information: This work is funded by Samsung Electronics (2020-11-1553). Publisher Copyright: {\textcopyright} 2021 JSAP.; 35th Symposium on VLSI Circuits, VLSI Circuits 2021 ; Conference date: 13-06-2021 Through 19-06-2021",

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doi = "10.23919/VLSICircuits52068.2021.9492519",

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Lee, S, Park, S, Kim, Y & Chae, Y 2021, A 0.6V 86.5dB-DR 40kHz-BW Inverter-Based Continuous-Time Delta-Sigma Modulator with PVT-Robust Body-Biasing Technique. in 2021 Symposium on VLSI Circuits, VLSI Circuits 2021., 9492519, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2021-June, Institute of Electrical and Electronics Engineers Inc., 35th Symposium on VLSI Circuits, VLSI Circuits 2021, Virutal, Online, 21/6/13. https://doi.org/10.23919/VLSICircuits52068.2021.9492519

A 0.6V 86.5dB-DR 40kHz-BW Inverter-Based Continuous-Time Delta-Sigma Modulator with PVT-Robust Body-Biasing Technique. / Lee, Sangwoo; Park, Sungsik; Kim, Yunhong et al.

2021 Symposium on VLSI Circuits, VLSI Circuits 2021. Institute of Electrical and Electronics Engineers Inc., 2021. 9492519 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2021-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - This paper presents a body-biasing technique for an energy-efficient inverter-based integrator that significantly improves the PVT robustness of the integrators in sub-1V continuous-time delta-sigma modulators (CTDSMs). A prototype CTDSM with the body-biasing technique is implemented in a 28 nm CMOS process and achieves 83 dB SNDR, 84 dB SNR, and 86.5 dB DR in a 40-kHz bandwidth, while consuming only 33.6 μW from a 0.6 V supply. It achieves a Schreier FoM of 177.3 dB.

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Lee S, Park S, Kim Y, Chae Y. A 0.6V 86.5dB-DR 40kHz-BW Inverter-Based Continuous-Time Delta-Sigma Modulator with PVT-Robust Body-Biasing Technique. In 2021 Symposium on VLSI Circuits, VLSI Circuits 2021. Institute of Electrical and Electronics Engineers Inc. 2021. 9492519. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.23919/VLSICircuits52068.2021.9492519

A 0.6V 86.5dB-DR 40kHz-BW Inverter-Based Continuous-Time Delta-Sigma Modulator with PVT-Robust Body-Biasing Technique

Abstract

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Bibliographical note

All Science Journal Classification (ASJC) codes

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