A 0.7-dB NF, +8.2-dBm IIP3 CMOS low noise amplifier using frequency selective feedback

Tae Hwan Jin, Hong Gul Han, Tae Wook Kim

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

A CMOS amplifier employing the frequency selective feedback technique using a shunt feedback capacitor is designed and measured. The proposed amplifier can achieve a high IIP3 (input referred third-order intercept point) by reducing the third- and second-order nonlinearity contributions to the IMD3 (third-order intermodulation distortion), which is accomplished using a capacitor as the frequency selective element. Also, the shunt feedback capacitor improves the noise performance of the amplifier. By applying the technique to a cascode LNA using 0.18-μm CMOS technology, we obtain the NF of 0.7 dB, an IIP3 of +8.2 dBm, and a gain of 15.1 dB at 14.4 mW of power consumption at 900 MHz.

Original languageEnglish
Pages (from-to)21-37
Number of pages17
JournalInternational Journal of Circuit Theory and Applications
Volume44
Issue number1
DOIs
Publication statusPublished - 2016 Jan 1

Fingerprint

Low Noise Amplifier
Low noise amplifiers
Capacitor
Capacitors
Feedback
Intermodulation distortion
Intercept
Power Consumption
Electric power utilization
Nonlinearity

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

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A 0.7-dB NF, +8.2-dBm IIP3 CMOS low noise amplifier using frequency selective feedback. / Jin, Tae Hwan; Han, Hong Gul; Kim, Tae Wook.

In: International Journal of Circuit Theory and Applications, Vol. 44, No. 1, 01.01.2016, p. 21-37.

Research output: Contribution to journalArticle

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