# A 0.9-V 28-MHz Highly Digital CMOS Dual-RC Frequency Reference With ±200 ppm Inaccuracy From -40 °C to 85 °C

Woojun Choi, Jan Angevare, Injun Park, Kofi A.A. Makinwa, Youngcheol Chae

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2 Citations (Scopus)

## Abstract

This article presents an energy-efficient dual- $RC$ frequency reference intended for wireless sensor nodes. It consists of a digital frequency-locked loop (FLL) in which the frequency of a digitally controlled oscillator (DCO) is locked to a temperature-independent phase shift derived from two different $RC$ poly-phase filters (PPFs). Phase shifts with complementary temperature coefficients (TCs) are generated by using PPFs made from different resistor types (p-poly and silicided p-poly). The phase shift of each filter is determined by a zero-crossing (ZC) detector and then digitized by a digital phase-domain $\Delta \Sigma$ modulator ( $\Phi$ - $\Delta \Sigma \text{M}$ ). The results are then combined in the digital domain via fixed polynomials to produce a temperature-independent phase shift. This highly digital architecture enables the use of a sub-1-V supply voltage and enhances energy and area efficiency. The 28-MHz frequency reference occupies 0.06 mm2 in a 65-nm CMOS process. It achieves a period jitter of 7 ps ( $1\sigma$ ) and draws $142~\mu \text{W}$ from a 0.9-V supply, which corresponds to an energy consumption of 5 pJ/cycle. Furthermore, it achieves ±200 ppm inaccuracy from $- 40\,\,^\circ \text{C}$ to $85~^\circ \text{C}$ after a two-point trim.

Original language English 2418-2428 11 IEEE Journal of Solid-State Circuits 57 8 https://doi.org/10.1109/JSSC.2021.3135939 Published - 2022 Aug 1

### Bibliographical note

Funding Information:
This work was supported in part by the Samsung Electronics Company Ltd., and in part by the National Research Foundation of Korea (NRF) Grant funded by the Korean Government (NRF-2016-Global Ph.D. Fellowship Program)