A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR with Path Mismatch Tracking Loop in a 28-nm CMOS Technology

Min Seong Choo, Kwanseo Park, Han Gon Ko, Sung Yong Cho, Kwangho Lee, Deog Kyoon Jeong

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)

Abstract

A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit half-rate all-digital injection-locked clock and data recovery (ILCDR) with a path mismatch tracking (PMT) loop is presented. When injection timing is not perfectly aligned with the phase of the oscillator, the timing margin of the data sampler is reduced, resulting in the degradation of jitter tolerance (JTOL) performance. The proposed ILCDR achieves robust injection behavior over path mismatch variations by correlating the error information from the phase detector (PD) in the conventional phase-locked loop (PLL)-based CDR with the polarity of the data transition, thereby adapting the path delay of the injection pulse and placing it at the optimum timing. Fabricated in 28-nm CMOS technology, the proposed ILCDR occupies 0.03 mm2 and consumes 12.8 mW at 10 Gb/s with a 0.9-V supply voltage. The measured JTOL is 1 UIpp at 31 MHz with the target bit error rate (BER) of 10-12 in the presence of the initial path delay mismatch.

Original languageEnglish
Article number8781914
Pages (from-to)2812-2822
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume54
Issue number10
DOIs
Publication statusPublished - 2019 Oct

Bibliographical note

Publisher Copyright:
© 1966-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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