A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology

Jinsoo Rhim, Kwang Chun Choi, Woo Young Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper reports a 10-Gb/s power and area efficient clock and data recovery circuit implemented in 65-nm CMOS technology. CMOS static circuits are used as much as possible so that the power consumption and the chip area can be minimized. In order to alleviate the supply sensitivity of CMOS static circuits, a supply-regulator is implemented. At 10-Gb/s, the clock and data recovery circuit consumes 5-mW of power and occupies 0.0075mm2 of area.

Original languageEnglish
Title of host publicationISOCC 2012 - 2012 International SoC Design Conference
Pages104-107
Number of pages4
DOIs
Publication statusPublished - 2012 Dec 1
Event2012 International SoC Design Conference, ISOCC 2012 - Jeju Island, Korea, Republic of
Duration: 2012 Nov 42012 Nov 7

Publication series

NameISOCC 2012 - 2012 International SoC Design Conference

Other

Other2012 International SoC Design Conference, ISOCC 2012
CountryKorea, Republic of
CityJeju Island
Period12/11/412/11/7

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology'. Together they form a unique fingerprint.

  • Cite this

    Rhim, J., Choi, K. C., & Choi, W. Y. (2012). A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology. In ISOCC 2012 - 2012 International SoC Design Conference (pp. 104-107). [6407050] (ISOCC 2012 - 2012 International SoC Design Conference). https://doi.org/10.1109/ISOCC.2012.6407050