A 100 nm copper/low-K bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications

Geoffrey C.F. Yeap, J. Chen, P. Grudowski, Y. Jeon, Y. Shiho, W. Qi, S. Jallepalli, N. Ramani, K. Hellig, L. Vishnubhotla, T. Luo, H. Tseng, Y. Du, S. Lim, P. Abramowitz, C. Reddy, S. Parihar, R. Singh, M. Wright, K. PattersonN. Benavides, D. Bonser, T. V. Gompel, J. Conner, J. J. Lee, M. Rendon, D. Hall, A. Nghiem, R. Stout, K. Weidemann, A. Duvallet, J. Alvis, D. Dyer, D. Burnett, P. Ingersoll, K. Wimmer, S. Veeraraghavan, M. Foisy, M. Hall, J. Pellerin, Dirk Wristers, M. Woo, C. Lage

Research output: Contribution to conferencePaper

16 Citations (Scopus)

Abstract

We report a 100 nm modular bulk CMOS technology platform with multi Vt and multi gate oxide integrated transistors that enables device and circuit co-design techniques (e.g., well biasing and power down/reduction) for low standby power (LSP), high performance (HP), high speed (HS), and RF/Analog system on chip (SoC) applications. The transistor performances are comparable or better than recently reported data at the 100 nm technology node (see Table 1). This technology also features an all-layer copper/low-k (< 3.0) interlayer dielectric (ILD) backend for speed improvement and dynamic power reduction.

Original languageEnglish
Pages16-17
Number of pages2
Publication statusPublished - 2002
Event2002 Symposium on VLSI Technology Digest of Technical Papers - Honolulu, HI, United States
Duration: 2002 Jun 112002 Jun 13

Other

Other2002 Symposium on VLSI Technology Digest of Technical Papers
CountryUnited States
CityHonolulu, HI
Period02/6/1102/6/13

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Yeap, G. C. F., Chen, J., Grudowski, P., Jeon, Y., Shiho, Y., Qi, W., Jallepalli, S., Ramani, N., Hellig, K., Vishnubhotla, L., Luo, T., Tseng, H., Du, Y., Lim, S., Abramowitz, P., Reddy, C., Parihar, S., Singh, R., Wright, M., ... Lage, C. (2002). A 100 nm copper/low-K bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications. 16-17. Paper presented at 2002 Symposium on VLSI Technology Digest of Technical Papers, Honolulu, HI, United States.