Abstract
This paper describes a 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with a 256-level phase resolution using only 4-phase reference clock. A novel scheme is proposed to enhance the phase resolution with little additional power consumption and chip area. A digitally-controlled delay buffer having a variable delay tunes output phase finely for a higher resolution. A prototype chip was fabricated with 0.18 μm CMOS technology. In the measurement, the CDR has ±400ppm frequency offset tolerance and a flat jitter performance for wide variations of delay buffer. The power consumption of the CDR core is 17.8mW with 1.8V supply and the core occupies 255 μm × 165 μm.
| Original language | English |
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| Title of host publication | ISCAS 2006 |
| Subtitle of host publication | 2006 IEEE International Symposium on Circuits and Systems, Proceedings |
| Pages | 2113-2116 |
| Number of pages | 4 |
| Publication status | Published - 2006 Dec 1 |
| Event | ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece Duration: 2006 May 21 → 2006 May 24 |
Publication series
| Name | Proceedings - IEEE International Symposium on Circuits and Systems |
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| ISSN (Print) | 0271-4310 |
Other
| Other | ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems |
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| Country | Greece |
| City | Kos |
| Period | 06/5/21 → 06/5/24 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
Seong, C. K., Lee, S. W., & Choi, W. Y. (2006). A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution. In ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings (pp. 2113-2116). [1693034] (Proceedings - IEEE International Symposium on Circuits and Systems).