A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution

Chang Kyung Seong; Seung Woo Lee; Woo Young Choi

A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution

Chang Kyung Seong, Seung Woo Lee, Woo Young Choi

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

This paper describes a 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with a 256-level phase resolution using only 4-phase reference clock. A novel scheme is proposed to enhance the phase resolution with little additional power consumption and chip area. A digitally-controlled delay buffer having a variable delay tunes output phase finely for a higher resolution. A prototype chip was fabricated with 0.18 μm CMOS technology. In the measurement, the CDR has ±400ppm frequency offset tolerance and a flat jitter performance for wide variations of delay buffer. The power consumption of the CDR core is 17.8mW with 1.8V supply and the core occupies 255 μm × 165 μm.

Original language	English
Title of host publication	ISCAS 2006
Subtitle of host publication	2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages	2113-2116
Number of pages	4
Publication status	Published - 2006
Event	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece Duration: 2006 May 21 → 2006 May 24

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Other

Other	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Country	Greece
City	Kos
Period	06/5/21 → 06/5/24

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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title = "A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution",

abstract = "This paper describes a 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with a 256-level phase resolution using only 4-phase reference clock. A novel scheme is proposed to enhance the phase resolution with little additional power consumption and chip area. A digitally-controlled delay buffer having a variable delay tunes output phase finely for a higher resolution. A prototype chip was fabricated with 0.18 μm CMOS technology. In the measurement, the CDR has ±400ppm frequency offset tolerance and a flat jitter performance for wide variations of delay buffer. The power consumption of the CDR core is 17.8mW with 1.8V supply and the core occupies 255 μm × 165 μm.",

author = "Seong, {Chang Kyung} and Lee, {Seung Woo} and Choi, {Woo Young}",

year = "2006",

language = "English",

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series = "Proceedings - IEEE International Symposium on Circuits and Systems",

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Seong, CK, Lee, SW & Choi, WY 2006, A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution. in ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings., 1693034, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 2113-2116, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, 06/5/21.

A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution. / Seong, Chang Kyung; Lee, Seung Woo; Choi, Woo Young.

ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. p. 2113-2116 1693034 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - This paper describes a 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with a 256-level phase resolution using only 4-phase reference clock. A novel scheme is proposed to enhance the phase resolution with little additional power consumption and chip area. A digitally-controlled delay buffer having a variable delay tunes output phase finely for a higher resolution. A prototype chip was fabricated with 0.18 μm CMOS technology. In the measurement, the CDR has ±400ppm frequency offset tolerance and a flat jitter performance for wide variations of delay buffer. The power consumption of the CDR core is 17.8mW with 1.8V supply and the core occupies 255 μm × 165 μm.

AB - This paper describes a 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with a 256-level phase resolution using only 4-phase reference clock. A novel scheme is proposed to enhance the phase resolution with little additional power consumption and chip area. A digitally-controlled delay buffer having a variable delay tunes output phase finely for a higher resolution. A prototype chip was fabricated with 0.18 μm CMOS technology. In the measurement, the CDR has ±400ppm frequency offset tolerance and a flat jitter performance for wide variations of delay buffer. The power consumption of the CDR core is 17.8mW with 1.8V supply and the core occupies 255 μm × 165 μm.

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