A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution

Chang Kyung Seong, Seung Woo Lee, Woo Young Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper describes a 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with a 256-level phase resolution using only 4-phase reference clock. A novel scheme is proposed to enhance the phase resolution with little additional power consumption and chip area. A digitally-controlled delay buffer having a variable delay tunes output phase finely for a higher resolution. A prototype chip was fabricated with 0.18 μm CMOS technology. In the measurement, the CDR has ±400ppm frequency offset tolerance and a flat jitter performance for wide variations of delay buffer. The power consumption of the CDR core is 17.8mW with 1.8V supply and the core occupies 255 μm × 165 μm.

Original languageEnglish
Title of host publicationISCAS 2006
Subtitle of host publication2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages2113-2116
Number of pages4
Publication statusPublished - 2006 Dec 1
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
Duration: 2006 May 212006 May 24

Other

OtherISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
CountryGreece
CityKos
Period06/5/2106/5/24

Fingerprint

Clock and data recovery circuits (CDR circuits)
Electric power utilization
Jitter
Clocks

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Seong, C. K., Lee, S. W., & Choi, W. Y. (2006). A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution. In ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings (pp. 2113-2116). [1693034]
Seong, Chang Kyung ; Lee, Seung Woo ; Choi, Woo Young. / A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution. ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. pp. 2113-2116
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Seong, CK, Lee, SW & Choi, WY 2006, A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution. in ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings., 1693034, pp. 2113-2116, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, 06/5/21.

A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution. / Seong, Chang Kyung; Lee, Seung Woo; Choi, Woo Young.

ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. p. 2113-2116 1693034.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - This paper describes a 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with a 256-level phase resolution using only 4-phase reference clock. A novel scheme is proposed to enhance the phase resolution with little additional power consumption and chip area. A digitally-controlled delay buffer having a variable delay tunes output phase finely for a higher resolution. A prototype chip was fabricated with 0.18 μm CMOS technology. In the measurement, the CDR has ±400ppm frequency offset tolerance and a flat jitter performance for wide variations of delay buffer. The power consumption of the CDR core is 17.8mW with 1.8V supply and the core occupies 255 μm × 165 μm.

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Seong CK, Lee SW, Choi WY. A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution. In ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. p. 2113-2116. 1693034