@inproceedings{56f76d9f9be44f66af4165a6863f2606,
title = "A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution",
abstract = "This paper describes a 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with a 256-level phase resolution using only 4-phase reference clock. A novel scheme is proposed to enhance the phase resolution with little additional power consumption and chip area. A digitally-controlled delay buffer having a variable delay tunes output phase finely for a higher resolution. A prototype chip was fabricated with 0.18 μm CMOS technology. In the measurement, the CDR has ±400ppm frequency offset tolerance and a flat jitter performance for wide variations of delay buffer. The power consumption of the CDR core is 17.8mW with 1.8V supply and the core occupies 255 μm × 165 μm.",
author = "Seong, {Chang Kyung} and Lee, {Seung Woo} and Choi, {Woo Young}",
year = "2006",
language = "English",
isbn = "0780393902",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
pages = "2113--2116",
booktitle = "ISCAS 2006",
note = "ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems ; Conference date: 21-05-2006 Through 24-05-2006",
}