Abstract
This paper describes a 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with a 256-level phase resolution using only 4-phase reference clock. A novel scheme is proposed to enhance the phase resolution with little additional power consumption and chip area. A digitally-controlled delay buffer having a variable delay tunes output phase finely for a higher resolution. A prototype chip was fabricated with 0.18 μm CMOS technology. In the measurement, the CDR has ±400ppm frequency offset tolerance and a flat jitter performance for wide variations of delay buffer. The power consumption of the CDR core is 17.8mW with 1.8V supply and the core occupies 255 μm × 165 μm.
| Original language | English |
|---|---|
| Title of host publication | ISCAS 2006 |
| Subtitle of host publication | 2006 IEEE International Symposium on Circuits and Systems, Proceedings |
| Pages | 2113-2116 |
| Number of pages | 4 |
| Publication status | Published - 2006 Dec 1 |
| Event | ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece Duration: 2006 May 21 → 2006 May 24 |
Other
| Other | ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems |
|---|---|
| Country | Greece |
| City | Kos |
| Period | 06/5/21 → 06/5/24 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
}
A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution. / Seong, Chang Kyung; Lee, Seung Woo; Choi, Woo Young.
ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. p. 2113-2116 1693034.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution
AU - Seong, Chang Kyung
AU - Lee, Seung Woo
AU - Choi, Woo Young
PY - 2006/12/1
Y1 - 2006/12/1
N2 - This paper describes a 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with a 256-level phase resolution using only 4-phase reference clock. A novel scheme is proposed to enhance the phase resolution with little additional power consumption and chip area. A digitally-controlled delay buffer having a variable delay tunes output phase finely for a higher resolution. A prototype chip was fabricated with 0.18 μm CMOS technology. In the measurement, the CDR has ±400ppm frequency offset tolerance and a flat jitter performance for wide variations of delay buffer. The power consumption of the CDR core is 17.8mW with 1.8V supply and the core occupies 255 μm × 165 μm.
AB - This paper describes a 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with a 256-level phase resolution using only 4-phase reference clock. A novel scheme is proposed to enhance the phase resolution with little additional power consumption and chip area. A digitally-controlled delay buffer having a variable delay tunes output phase finely for a higher resolution. A prototype chip was fabricated with 0.18 μm CMOS technology. In the measurement, the CDR has ±400ppm frequency offset tolerance and a flat jitter performance for wide variations of delay buffer. The power consumption of the CDR core is 17.8mW with 1.8V supply and the core occupies 255 μm × 165 μm.
UR - http://www.scopus.com/inward/record.url?scp=34547320386&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34547320386&partnerID=8YFLogxK
M3 - Conference contribution
SN - 0780393902
SN - 9780780393905
SP - 2113
EP - 2116
BT - ISCAS 2006
ER -