A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution

Chang Kyung Seong, Seung Woo Lee, Woo Young Choi

Research output: Contribution to journalArticle

Abstract

A new 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit is realized. To overcome jitter problems caused by the phase resolution limit, the CDR has two phase generation stages: coarse generation by a phase interpolator and fine generation by a variable delay buffer. The performance of the proposed CDR was verified by behavioral and transistor-level simulations. A prototype CDR chip fabricated with 0.18 μm CMOS process shows error-free operation for ±400 ppm frequency offset. The chip occupies 165 × 255 μm2 and consumes 17.8 mW.

Original languageEnglish
Pages (from-to)165-169
Number of pages5
JournalIEICE Transactions on Electronics
VolumeE90-C
Issue number1
DOIs
Publication statusPublished - 2007 Jan

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All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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