A 134μW 24kHz-BW 103.5d8-DR CT ΔΣ Modulator with Chopped Negative-R and Tri-Level FIR DAC

Moonhyung Jang; Changuk Lee; Youngcheol Chae

doi:10.1109/ISSCC19947.2020.9062904

A 134μW 24kHz-BW 103.5d8-DR CT ΔΣ Modulator with Chopped Negative-R and Tri-Level FIR DAC

Moonhyung Jang, Changuk Lee, Youngcheol Chae

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

Audio applications require a high-resolution ADC with a dynamic range (DR) of more than 100dB. A continuous-time delta-sigma modulator (CTDSM) is widely used to realize such ADCs and requires high energy efficiency for battery-powered devices [1-5]. This paper presents a more efficient, highly linear CTDSM architecture for audio applications. The first integrator of the CTDSM uses a chopped negative-R in conjunction with a tri-level FIR DAC to increase energy-efficiency. Non-idealities of an active-RC integrator are compensated using a negative-R at the virtual ground of the integrator, and the negative-R is then chopped to remove its 1/f noise at a notch frequency of the feedback FIR filter. A 6-tap, tri-level FIR DAC is realized with a resistive non-return-to-zero (NRZ) DAC whose inter-symbol-interference (ISI) is kept less than -120dB. As a result, this work achieves 99.4dB SNDR, 101dB SNR, 103.5dB DR, and 110.2dB SFDR in a 24kHz bandwidth while consuming only 134μW. This corresponds to a Schreier FoM of 186dB.

Original language	English
Title of host publication	2020 IEEE International Solid-State Circuits Conference, ISSCC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-3
Number of pages	3
ISBN (Electronic)	9781728132044
DOIs	https://doi.org/10.1109/ISSCC19947.2020.9062904
Publication status	Published - 2020 Feb
Event	2020 IEEE International Solid-State Circuits Conference, ISSCC 2020 - San Francisco, United States Duration: 2020 Feb 16 → 2020 Feb 20

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	2020-February
ISSN (Print)	0193-6530

Conference

Conference	2020 IEEE International Solid-State Circuits Conference, ISSCC 2020
Country/Territory	United States
City	San Francisco
Period	20/2/16 → 20/2/20

Bibliographical note

Publisher Copyright:
© 2020 IEEE.

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/ISSCC19947.2020.9062904

Cite this

Jang, M., Lee, C., & Chae, Y. (2020). A 134μW 24kHz-BW 103.5d8-DR CT ΔΣ Modulator with Chopped Negative-R and Tri-Level FIR DAC. In 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020 (pp. 1-3). [9062904] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 2020-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC19947.2020.9062904

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abstract = "Audio applications require a high-resolution ADC with a dynamic range (DR) of more than 100dB. A continuous-time delta-sigma modulator (CTDSM) is widely used to realize such ADCs and requires high energy efficiency for battery-powered devices [1-5]. This paper presents a more efficient, highly linear CTDSM architecture for audio applications. The first integrator of the CTDSM uses a chopped negative-R in conjunction with a tri-level FIR DAC to increase energy-efficiency. Non-idealities of an active-RC integrator are compensated using a negative-R at the virtual ground of the integrator, and the negative-R is then chopped to remove its 1/f noise at a notch frequency of the feedback FIR filter. A 6-tap, tri-level FIR DAC is realized with a resistive non-return-to-zero (NRZ) DAC whose inter-symbol-interference (ISI) is kept less than -120dB. As a result, this work achieves 99.4dB SNDR, 101dB SNR, 103.5dB DR, and 110.2dB SFDR in a 24kHz bandwidth while consuming only 134μW. This corresponds to a Schreier FoM of 186dB.",

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Jang, M, Lee, C & Chae, Y 2020, A 134μW 24kHz-BW 103.5d8-DR CT ΔΣ Modulator with Chopped Negative-R and Tri-Level FIR DAC. in 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020., 9062904, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 2020-February, Institute of Electrical and Electronics Engineers Inc., pp. 1-3, 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020, San Francisco, United States, 20/2/16. https://doi.org/10.1109/ISSCC19947.2020.9062904

A 134μW 24kHz-BW 103.5d8-DR CT ΔΣ Modulator with Chopped Negative-R and Tri-Level FIR DAC. / Jang, Moonhyung; Lee, Changuk; Chae, Youngcheol.

2020 IEEE International Solid-State Circuits Conference, ISSCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 1-3 9062904 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 2020-February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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PY - 2020/2

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N2 - Audio applications require a high-resolution ADC with a dynamic range (DR) of more than 100dB. A continuous-time delta-sigma modulator (CTDSM) is widely used to realize such ADCs and requires high energy efficiency for battery-powered devices [1-5]. This paper presents a more efficient, highly linear CTDSM architecture for audio applications. The first integrator of the CTDSM uses a chopped negative-R in conjunction with a tri-level FIR DAC to increase energy-efficiency. Non-idealities of an active-RC integrator are compensated using a negative-R at the virtual ground of the integrator, and the negative-R is then chopped to remove its 1/f noise at a notch frequency of the feedback FIR filter. A 6-tap, tri-level FIR DAC is realized with a resistive non-return-to-zero (NRZ) DAC whose inter-symbol-interference (ISI) is kept less than -120dB. As a result, this work achieves 99.4dB SNDR, 101dB SNR, 103.5dB DR, and 110.2dB SFDR in a 24kHz bandwidth while consuming only 134μW. This corresponds to a Schreier FoM of 186dB.

AB - Audio applications require a high-resolution ADC with a dynamic range (DR) of more than 100dB. A continuous-time delta-sigma modulator (CTDSM) is widely used to realize such ADCs and requires high energy efficiency for battery-powered devices [1-5]. This paper presents a more efficient, highly linear CTDSM architecture for audio applications. The first integrator of the CTDSM uses a chopped negative-R in conjunction with a tri-level FIR DAC to increase energy-efficiency. Non-idealities of an active-RC integrator are compensated using a negative-R at the virtual ground of the integrator, and the negative-R is then chopped to remove its 1/f noise at a notch frequency of the feedback FIR filter. A 6-tap, tri-level FIR DAC is realized with a resistive non-return-to-zero (NRZ) DAC whose inter-symbol-interference (ISI) is kept less than -120dB. As a result, this work achieves 99.4dB SNDR, 101dB SNR, 103.5dB DR, and 110.2dB SFDR in a 24kHz bandwidth while consuming only 134μW. This corresponds to a Schreier FoM of 186dB.

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Jang M, Lee C, Chae Y. A 134μW 24kHz-BW 103.5d8-DR CT ΔΣ Modulator with Chopped Negative-R and Tri-Level FIR DAC. In 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 1-3. 9062904. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC19947.2020.9062904

A 134μW 24kHz-BW 103.5d8-DR CT ΔΣ Modulator with Chopped Negative-R and Tri-Level FIR DAC

Abstract

Publication series

Conference

Bibliographical note

All Science Journal Classification (ASJC) codes

UN SDGs

Access to Document

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