Abstract
This article presents a low-power audio continuous-time delta-sigma modulator (CTDSM) that employs a chopped negative-R and a tri-level finite impulse-response (FIR) DAC. The noise of the first opamp is mitigated by using a negative-R at the virtual ground of the first integrator, and the negative-R is then chopped to remove the intrinsic ${1/f}$ noise of the negative-R. The highly linear feedback DAC is realized with a 6-tap tri-level FIR-DAC whose inter-symbol interference (ISI) is kept less than -120 dB. The CTDSM fabricated in 65-nm CMOS technology occupies an active area of 0.28 mm2. It achieves 99.4-dB SNDR, 101-dB SNR, 102.8-dB dynamic range (DR), and 110.2-dB SFDR in a 24-kHz bandwidth, while consuming only $134~\mu \text{W}$. This corresponds to a state-of-the-art figure-of-merit (FoM) of 185.3 dB.
| Original language | English |
|---|---|
| Article number | 9252136 |
| Pages (from-to) | 1761-1771 |
| Number of pages | 11 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 56 |
| Issue number | 6 |
| DOIs | |
| Publication status | Published - 2021 Jun |
Bibliographical note
Funding Information:Youngcheol Chae (Senior Member, IEEE) received the B.S., M.S., and Ph.D. degrees in electrical and electronic engineering from Yonsei University, Seoul, South Korea, in 2003, 2005, and 2009, respectively. From 2009 to 2011, he was a Post-Doctoral Researcher with Electronic Instrumentation Labo-ratory, Delft University of Technology, Delft, The Netherlands. Since 2012, he has been on the Fac-ulty at Yonsei University, where he is currently an Associate Professor. His work has focused on low-power data converters and high-performance sensor interfaces; this resulted in more than 90 technical articles and 30 patents. Dr. Chae is also a member of the Technical Program Committees of the International Solid-State Circuits Conference (ISSCC) and the Asian Solid-State Circuits Conference (A-SSCC). He received the Best Young Professor Award in Engineering from Yonsei University in 2018, the Haedong Young Engineer Award from the IEE Korea in 2017, the Outstanding Research Award of Yonsei University from 2017 to 2019, and the Outstanding Teaching Awards of Yonsei University in 2013 and 2014. He received a research grant from the Samsung Research Funding Center in 2017 and a VENI grant from the Dutch Technology Foundation STW in 2011. He has served as a Guest Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC) and a Distinguished Lecturer (DL) for the IEEE Solid-State Circuits Society (SSCS).
Funding Information:
Manuscript received May 26, 2020; revised August 22, 2020 and October 8, 2020; accepted October 8, 2020. Date of publication November 9, 2020; date of current version May 26, 2021. This article was approved by Guest Editor Shanthi Pavan. This work was supported in part by the National Research Foundation of Korea (NRF) Grant funded by the Korean Government (MSIT) under Grant 2018R1A4A1025986 and in part by Samsung Electronics. (Corresponding author: Youngcheol Chae.) The authors are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 03722, South Korea (e-mail: ychae@yonsei.ac.kr).
Publisher Copyright:
© 1966-2012 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering