A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL with Maximized Injection Strength Using Adjustment of Phase Domain Response

Min Seong Choo, Yeonggeun Song, Sung Yong Cho, Han Gon Ko, Kwanseo Park, Deog Kyoon Jeong

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

This brief presents an injection-locked PLL (ILPLL) that offers better jitter performance for high-speed clock generation. By analyzing and adjusting a phase domain response (PDR) of the injection-locked oscillator (ILO), the injection strength at the target frequency of 15 GHz is maximized with the lowest deterministic noise. In addition, a pulse generator that limits the maximum operating speed in the conventional ILPLL is removed to achieve the highest synthesizable clock frequency. Fabricated in 28-nm CMOS technology, the proposed ILPLL occupies an active area of 0.03 mm2 and dissipates 17.8 mW at 15 GHz with a 1.3-V supply voltage. The measured integrated jitter from 1 kHz to 40 MHz at the point of maximum injection strength is 213 fs and the corresponding reference spur level is-43 dBc.

Original languageEnglish
Article number8883248
Pages (from-to)1932-1936
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume66
Issue number12
DOIs
Publication statusPublished - 2019 Dec

Bibliographical note

Publisher Copyright:
© 2004-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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