A 1.5 v 2 GS/s 82.1 dB-SFDR Track and Hold Circuit Based on the Time-Divided Post-Distortion Cancelation Technique

Junyoung Jang; Youngcheol Chae; Tae Wook Kim

doi:10.1109/TCSII.2022.3204031

A 1.5 v 2 GS/s 82.1 dB-SFDR Track and Hold Circuit Based on the Time-Divided Post-Distortion Cancelation Technique

Junyoung Jang, Youngcheol Chae, Tae Wook Kim

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

This brief presents a track and hold (T/H) circuit for time-interleaved analog-To-digital converters based on a new linearization technique-time-divided post-distortion cancellation. Fabricated in 65 nm CMOS, it achieves 82.1 dB SFDR with a 700-mV near-Nyquist input at a clock speed of 2 GS/s, while drawing only 9 mW power from a 1.5-V supply. Compared to the previous state-of-The-Art circuits, this T/H circuit exhibits an energy-efficiency figure-of-merit improvement of 9.5 dB.

Original language	English
Pages (from-to)	4719-4723
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	69
Issue number	12
DOIs	https://doi.org/10.1109/TCSII.2022.3204031
Publication status	Published - 2022 Dec 1

Bibliographical note

Funding Information:
This work was supported by the Institute of Information & Communications Technology Planning & Evaluation (IITP) Grant funded by the Korea Government (MSIT) under Grant 2017-0-00418.

Publisher Copyright:
© 2004-2012 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/TCSII.2022.3204031

Cite this

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title = "A 1.5 v 2 GS/s 82.1 dB-SFDR Track and Hold Circuit Based on the Time-Divided Post-Distortion Cancelation Technique",

abstract = "This brief presents a track and hold (T/H) circuit for time-interleaved analog-To-digital converters based on a new linearization technique-time-divided post-distortion cancellation. Fabricated in 65 nm CMOS, it achieves 82.1 dB SFDR with a 700-mV near-Nyquist input at a clock speed of 2 GS/s, while drawing only 9 mW power from a 1.5-V supply. Compared to the previous state-of-The-Art circuits, this T/H circuit exhibits an energy-efficiency figure-of-merit improvement of 9.5 dB.",

author = "Junyoung Jang and Youngcheol Chae and Kim, {Tae Wook}",

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A 1.5 v 2 GS/s 82.1 dB-SFDR Track and Hold Circuit Based on the Time-Divided Post-Distortion Cancelation Technique

Abstract

Bibliographical note

All Science Journal Classification (ASJC) codes

UN SDGs

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