This brief presents a track and hold (T/H) circuit for time-interleaved analog-To-digital converters based on a new linearization technique-time-divided post-distortion cancellation. Fabricated in 65 nm CMOS, it achieves 82.1 dB SFDR with a 700-mV near-Nyquist input at a clock speed of 2 GS/s, while drawing only 9 mW power from a 1.5-V supply. Compared to the previous state-of-The-Art circuits, this T/H circuit exhibits an energy-efficiency figure-of-merit improvement of 9.5 dB.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2022 Dec 1|
Bibliographical noteFunding Information:
This work was supported by the Institute of Information & Communications Technology Planning & Evaluation (IITP) Grant funded by the Korea Government (MSIT) under Grant 2017-0-00418.
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering