A 1.8-3.2-GHz fully differential GaAs MESFET PLL

Tae Sik Cheung; Bhum Cheol Lee; Eun Chang Choi; Woo Young Choi

doi:10.1109/4.913738

A 1.8-3.2-GHz fully differential GaAs MESFET PLL

Tae Sik Cheung, Bhum Cheol Lee, Eun Chang Choi, Woo Young Choi

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

A 1.8-3.2-GHz fully differential phase-locked loop (PLL) is realized for asynchronous transfer mode clock generation applications. The PLL includes a new differential voltage controlled oscillator with the wide tuning range of 1.74 ∼ 3.40 GHz and a new differential charge pump with improved hold characteristics. The PLL is implemented with 0.5-μm GaAs MESFET technology. The experimental results show that the proposed PLL has a lock range of 1.8 ∼ 3.2 GHz and its output RMS jitter is at most 5.0 ps (0.015 UI) at 3.2 GHz.

Original language	English
Pages (from-to)	605-610
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	36
Issue number	4
DOIs	https://doi.org/10.1109/4.913738
Publication status	Published - 2001

Bibliographical note

Funding Information:
Manuscript received May 3, 2000; revised December 6, 2000. This work was supported by the Korean Ministry of Information and Communications and by the Brain Korea 21 Project.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/4.913738

Cite this

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title = "A 1.8-3.2-GHz fully differential GaAs MESFET PLL",

abstract = "A 1.8-3.2-GHz fully differential phase-locked loop (PLL) is realized for asynchronous transfer mode clock generation applications. The PLL includes a new differential voltage controlled oscillator with the wide tuning range of 1.74 ∼ 3.40 GHz and a new differential charge pump with improved hold characteristics. The PLL is implemented with 0.5-μm GaAs MESFET technology. The experimental results show that the proposed PLL has a lock range of 1.8 ∼ 3.2 GHz and its output RMS jitter is at most 5.0 ps (0.015 UI) at 3.2 GHz.",

author = "Cheung, {Tae Sik} and Lee, {Bhum Cheol} and Choi, {Eun Chang} and Choi, {Woo Young}",

note = "Funding Information: Manuscript received May 3, 2000; revised December 6, 2000. This work was supported by the Korean Ministry of Information and Communications and by the Brain Korea 21 Project.",

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T1 - A 1.8-3.2-GHz fully differential GaAs MESFET PLL

AU - Cheung, Tae Sik

AU - Lee, Bhum Cheol

AU - Choi, Eun Chang

AU - Choi, Woo Young

N1 - Funding Information: Manuscript received May 3, 2000; revised December 6, 2000. This work was supported by the Korean Ministry of Information and Communications and by the Brain Korea 21 Project.

PY - 2001

Y1 - 2001

N2 - A 1.8-3.2-GHz fully differential phase-locked loop (PLL) is realized for asynchronous transfer mode clock generation applications. The PLL includes a new differential voltage controlled oscillator with the wide tuning range of 1.74 ∼ 3.40 GHz and a new differential charge pump with improved hold characteristics. The PLL is implemented with 0.5-μm GaAs MESFET technology. The experimental results show that the proposed PLL has a lock range of 1.8 ∼ 3.2 GHz and its output RMS jitter is at most 5.0 ps (0.015 UI) at 3.2 GHz.

AB - A 1.8-3.2-GHz fully differential phase-locked loop (PLL) is realized for asynchronous transfer mode clock generation applications. The PLL includes a new differential voltage controlled oscillator with the wide tuning range of 1.74 ∼ 3.40 GHz and a new differential charge pump with improved hold characteristics. The PLL is implemented with 0.5-μm GaAs MESFET technology. The experimental results show that the proposed PLL has a lock range of 1.8 ∼ 3.2 GHz and its output RMS jitter is at most 5.0 ps (0.015 UI) at 3.2 GHz.

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A 1.8-3.2-GHz fully differential GaAs MESFET PLL

Abstract

Bibliographical note

All Science Journal Classification (ASJC) codes

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