A 1.8-3.2-GHz fully differential GaAs MESFET PLL

Tae Sik Cheung, Bhum Cheol Lee, Eun Chang Choi, Woo Young Choi

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

A 1.8-3.2-GHz fully differential phase-locked loop (PLL) is realized for asynchronous transfer mode clock generation applications. The PLL includes a new differential voltage controlled oscillator with the wide tuning range of 1.74 ∼ 3.40 GHz and a new differential charge pump with improved hold characteristics. The PLL is implemented with 0.5-μm GaAs MESFET technology. The experimental results show that the proposed PLL has a lock range of 1.8 ∼ 3.2 GHz and its output RMS jitter is at most 5.0 ps (0.015 UI) at 3.2 GHz.

Original languageEnglish
Pages (from-to)605-610
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume36
Issue number4
DOIs
Publication statusPublished - 2001 Jan 1

Fingerprint

Phase locked loops
Asynchronous transfer mode
Variable frequency oscillators
Jitter
Clocks
Tuning
Pumps

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Cheung, Tae Sik ; Lee, Bhum Cheol ; Choi, Eun Chang ; Choi, Woo Young. / A 1.8-3.2-GHz fully differential GaAs MESFET PLL. In: IEEE Journal of Solid-State Circuits. 2001 ; Vol. 36, No. 4. pp. 605-610.
@article{00e58935518a4f05b8c3ba134341ffa9,
title = "A 1.8-3.2-GHz fully differential GaAs MESFET PLL",
abstract = "A 1.8-3.2-GHz fully differential phase-locked loop (PLL) is realized for asynchronous transfer mode clock generation applications. The PLL includes a new differential voltage controlled oscillator with the wide tuning range of 1.74 ∼ 3.40 GHz and a new differential charge pump with improved hold characteristics. The PLL is implemented with 0.5-μm GaAs MESFET technology. The experimental results show that the proposed PLL has a lock range of 1.8 ∼ 3.2 GHz and its output RMS jitter is at most 5.0 ps (0.015 UI) at 3.2 GHz.",
author = "Cheung, {Tae Sik} and Lee, {Bhum Cheol} and Choi, {Eun Chang} and Choi, {Woo Young}",
year = "2001",
month = "1",
day = "1",
doi = "10.1109/4.913738",
language = "English",
volume = "36",
pages = "605--610",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "4",

}

A 1.8-3.2-GHz fully differential GaAs MESFET PLL. / Cheung, Tae Sik; Lee, Bhum Cheol; Choi, Eun Chang; Choi, Woo Young.

In: IEEE Journal of Solid-State Circuits, Vol. 36, No. 4, 01.01.2001, p. 605-610.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A 1.8-3.2-GHz fully differential GaAs MESFET PLL

AU - Cheung, Tae Sik

AU - Lee, Bhum Cheol

AU - Choi, Eun Chang

AU - Choi, Woo Young

PY - 2001/1/1

Y1 - 2001/1/1

N2 - A 1.8-3.2-GHz fully differential phase-locked loop (PLL) is realized for asynchronous transfer mode clock generation applications. The PLL includes a new differential voltage controlled oscillator with the wide tuning range of 1.74 ∼ 3.40 GHz and a new differential charge pump with improved hold characteristics. The PLL is implemented with 0.5-μm GaAs MESFET technology. The experimental results show that the proposed PLL has a lock range of 1.8 ∼ 3.2 GHz and its output RMS jitter is at most 5.0 ps (0.015 UI) at 3.2 GHz.

AB - A 1.8-3.2-GHz fully differential phase-locked loop (PLL) is realized for asynchronous transfer mode clock generation applications. The PLL includes a new differential voltage controlled oscillator with the wide tuning range of 1.74 ∼ 3.40 GHz and a new differential charge pump with improved hold characteristics. The PLL is implemented with 0.5-μm GaAs MESFET technology. The experimental results show that the proposed PLL has a lock range of 1.8 ∼ 3.2 GHz and its output RMS jitter is at most 5.0 ps (0.015 UI) at 3.2 GHz.

UR - http://www.scopus.com/inward/record.url?scp=0035309965&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0035309965&partnerID=8YFLogxK

U2 - 10.1109/4.913738

DO - 10.1109/4.913738

M3 - Article

AN - SCOPUS:0035309965

VL - 36

SP - 605

EP - 610

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 4

ER -