A 1.8-3.2-GHz fully differential phase-locked loop (PLL) is realized for asynchronous transfer mode clock generation applications. The PLL includes a new differential voltage controlled oscillator with the wide tuning range of 1.74 ∼ 3.40 GHz and a new differential charge pump with improved hold characteristics. The PLL is implemented with 0.5-μm GaAs MESFET technology. The experimental results show that the proposed PLL has a lock range of 1.8 ∼ 3.2 GHz and its output RMS jitter is at most 5.0 ps (0.015 UI) at 3.2 GHz.
Bibliographical noteFunding Information:
Manuscript received May 3, 2000; revised December 6, 2000. This work was supported by the Korean Ministry of Information and Communications and by the Brain Korea 21 Project.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering