A 1V 7.8mW 15.6Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4

Woojun Choi; Taewoong Kim; Jongjoo Shim; Hyungsoo Kim; Gunhee Han; Youngcheol Chae

doi:10.1109/ISSCC.2017.7870431

A 1V 7.8mW 15.6Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4

Woojun Choi, Taewoong Kim, Jongjoo Shim, Hyungsoo Kim, Gunhee Han, Youngcheol Chae

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

Mobile DRAMs are essential to support memory-intensive operations for smartphones and tablet PCs [1, 2]. Since mobile DRAM standard (LPDDR), for the next generation, targets the speed specification of 51.2GB/s, its I/O interface demands high bandwidth, low power and high efficiency. Single-ended signaling has been used for LPDDR interfaces due to 100% pin efficiency. However, as the data rate increases simultaneous switching noise (SSN) limits the bandwidth. Although differential signaling can effectively remove SSN, it suffers from a pin efficiency drop of 50%, requiring that the signal bandwidth be doubled. To address this issue, differential coding schemes that encode signals over multiple channels have been explored to achieve pin efficiency and SSN robustness [4]. This paper presents a 1V 15.6Gb/s C-PHY transceiver using tri-level signaling that consumes only 7.8mW, resulting in an energy-efficiency of 0.5pJ/b. Such a high efficiency is achieved by the use of a tri-level signaling, which is from C-PHY encoding scheme of MIPI alliance standards, in combination with an active-ground tri-level transmitter and a crosstalk-cancelled low-power receiver.

Original language	English
Title of host publication	2017 IEEE International Solid-State Circuits Conference, ISSCC 2017
Editors	Laura C. Fujino
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	402-403
Number of pages	2
ISBN (Electronic)	9781509037575
DOIs	https://doi.org/10.1109/ISSCC.2017.7870431
Publication status	Published - 2017 Mar 2
Event	64th IEEE International Solid-State Circuits Conference, ISSCC 2017 - San Francisco, United States Duration: 2017 Feb 5 → 2017 Feb 9

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	60
ISSN (Print)	0193-6530

Other

Other	64th IEEE International Solid-State Circuits Conference, ISSCC 2017
Country	United States
City	San Francisco
Period	17/2/5 → 17/2/9

Bibliographical note

Funding Information:
This research was supported by the Ministry of Science, ICT and Future Planning, Korea, under the "ICT Consilience Creative Program" (IITP-R0346-16-1008) supervised by the IITP.

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

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Choi, W., Kim, T., Shim, J., Kim, H., Han, G., & Chae, Y. (2017). A 1V 7.8mW 15.6Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4. In L. C. Fujino (Ed.), 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017 (pp. 402-403). [7870431] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 60). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2017.7870431

Choi, Woojun ; Kim, Taewoong ; Shim, Jongjoo ; Kim, Hyungsoo ; Han, Gunhee ; Chae, Youngcheol. / A 1V 7.8mW 15.6Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4. 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017. editor / Laura C. Fujino. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 402-403 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

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abstract = "Mobile DRAMs are essential to support memory-intensive operations for smartphones and tablet PCs [1, 2]. Since mobile DRAM standard (LPDDR), for the next generation, targets the speed specification of 51.2GB/s, its I/O interface demands high bandwidth, low power and high efficiency. Single-ended signaling has been used for LPDDR interfaces due to 100% pin efficiency. However, as the data rate increases simultaneous switching noise (SSN) limits the bandwidth. Although differential signaling can effectively remove SSN, it suffers from a pin efficiency drop of 50%, requiring that the signal bandwidth be doubled. To address this issue, differential coding schemes that encode signals over multiple channels have been explored to achieve pin efficiency and SSN robustness [4]. This paper presents a 1V 15.6Gb/s C-PHY transceiver using tri-level signaling that consumes only 7.8mW, resulting in an energy-efficiency of 0.5pJ/b. Such a high efficiency is achieved by the use of a tri-level signaling, which is from C-PHY encoding scheme of MIPI alliance standards, in combination with an active-ground tri-level transmitter and a crosstalk-cancelled low-power receiver.",

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Choi, W, Kim, T, Shim, J, Kim, H, Han, G & Chae, Y 2017, A 1V 7.8mW 15.6Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4. in LC Fujino (ed.), 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017., 7870431, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 60, Institute of Electrical and Electronics Engineers Inc., pp. 402-403, 64th IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, United States, 17/2/5. https://doi.org/10.1109/ISSCC.2017.7870431

A 1V 7.8mW 15.6Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4. / Choi, Woojun; Kim, Taewoong; Shim, Jongjoo; Kim, Hyungsoo; Han, Gunhee ; Chae, Youngcheol.

2017 IEEE International Solid-State Circuits Conference, ISSCC 2017. ed. / Laura C. Fujino. Institute of Electrical and Electronics Engineers Inc., 2017. p. 402-403 7870431 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 60).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Choi W, Kim T, Shim J, Kim H, Han G , Chae Y. A 1V 7.8mW 15.6Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4. In Fujino LC, editor, 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 402-403. 7870431. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2017.7870431