TY - GEN
T1 - A 1V 7.8mW 15.6Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4
AU - Choi, Woojun
AU - Kim, Taewoong
AU - Shim, Jongjoo
AU - Kim, Hyungsoo
AU - Han, Gunhee
AU - Chae, Youngcheol
PY - 2017/3/2
Y1 - 2017/3/2
N2 - Mobile DRAMs are essential to support memory-intensive operations for smartphones and tablet PCs [1, 2]. Since mobile DRAM standard (LPDDR), for the next generation, targets the speed specification of 51.2GB/s, its I/O interface demands high bandwidth, low power and high efficiency. Single-ended signaling has been used for LPDDR interfaces due to 100% pin efficiency. However, as the data rate increases simultaneous switching noise (SSN) limits the bandwidth. Although differential signaling can effectively remove SSN, it suffers from a pin efficiency drop of 50%, requiring that the signal bandwidth be doubled. To address this issue, differential coding schemes that encode signals over multiple channels have been explored to achieve pin efficiency and SSN robustness [4]. This paper presents a 1V 15.6Gb/s C-PHY transceiver using tri-level signaling that consumes only 7.8mW, resulting in an energy-efficiency of 0.5pJ/b. Such a high efficiency is achieved by the use of a tri-level signaling, which is from C-PHY encoding scheme of MIPI alliance standards, in combination with an active-ground tri-level transmitter and a crosstalk-cancelled low-power receiver.
AB - Mobile DRAMs are essential to support memory-intensive operations for smartphones and tablet PCs [1, 2]. Since mobile DRAM standard (LPDDR), for the next generation, targets the speed specification of 51.2GB/s, its I/O interface demands high bandwidth, low power and high efficiency. Single-ended signaling has been used for LPDDR interfaces due to 100% pin efficiency. However, as the data rate increases simultaneous switching noise (SSN) limits the bandwidth. Although differential signaling can effectively remove SSN, it suffers from a pin efficiency drop of 50%, requiring that the signal bandwidth be doubled. To address this issue, differential coding schemes that encode signals over multiple channels have been explored to achieve pin efficiency and SSN robustness [4]. This paper presents a 1V 15.6Gb/s C-PHY transceiver using tri-level signaling that consumes only 7.8mW, resulting in an energy-efficiency of 0.5pJ/b. Such a high efficiency is achieved by the use of a tri-level signaling, which is from C-PHY encoding scheme of MIPI alliance standards, in combination with an active-ground tri-level transmitter and a crosstalk-cancelled low-power receiver.
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U2 - 10.1109/ISSCC.2017.7870431
DO - 10.1109/ISSCC.2017.7870431
M3 - Conference contribution
AN - SCOPUS:85016335199
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 402
EP - 403
BT - 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017
A2 - Fujino, Laura C.
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 64th IEEE International Solid-State Circuits Conference, ISSCC 2017
Y2 - 5 February 2017 through 9 February 2017
ER -