A 2-D compaction method using macro block for post-silicon validation

Won Jung, Hyunggoy Oh, Dongho Kang, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)


The post-silicon validation has been an important step as the complexity of system on chip (SoC) increases. Conventional trace buffer based debug methods offer consecutive observability and real time debug, but the size constraint of the trace buffer still is a challenge. The proposed method uses 2-D compaction for expanding the depth of observation window in a trace buffer. Moreover, the macro block, which is used with 2-D compaction, offers tolerance to various error patterns as a virtual window. The errors identified by the 2-D compaction using the macro block are selectively captured by using the new tag map. The experimental results show that the proposed method enables the reduction of error misidentification.

Original languageEnglish
Title of host publicationISOCC 2015 - International SoC Design Conference
Subtitle of host publicationSoC for Internet of Everything (IoE)
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages2
ISBN (Electronic)9781467393089
Publication statusPublished - 2016 Feb 8
Event12th International SoC Design Conference, ISOCC 2015 - Gyeongju, Korea, Republic of
Duration: 2015 Nov 22015 Nov 5

Publication series

NameISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)


Other12th International SoC Design Conference, ISOCC 2015
Country/TerritoryKorea, Republic of

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials


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