A 2-Gbps CMOS adaptive line equalizer

Jae Wook Lee, Bhum Cheol Lee, Woo Young Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A 2-Gbps line equalizer circuit is realized with 0.25 μm CMOS technology. The equalizer is made of input stage buffer, limiter and square difference circuits. The limiter has replica-feedback limiting amplifiers, which do not require common mode feedback. Successful equalization is demonstrated for signals transmitted over 1.5m long PCB trace.

Original languageEnglish
Title of host publicationProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
Pages244-247
Number of pages4
Publication statusPublished - 2004 Dec 1
EventProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits - Fukuoka, Japan
Duration: 2004 Aug 42004 Aug 5

Publication series

NameProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

Other

OtherProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
CountryJapan
CityFukuoka
Period04/8/404/8/5

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Lee, J. W., Lee, B. C., & Choi, W. Y. (2004). A 2-Gbps CMOS adaptive line equalizer. In Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (pp. 244-247). (Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits).