A 2 mW, 50 dB DR, 10 MHz BW 5× interleaved bandpass delta-sigma modulator at 50 MHz if

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Abstract

A 2 mW 50 dB-DR 10 MHz-BW bandpass (BP) delta-sigma (ΔΣ) modulator for a digital-IF receiver is presented. It is based on a power-efficient time-interleaved (TI) architecture, which uses a recursive loop and a feed-forward topology. To further improve its power-efficiency, the ADC employs inverter-based OTAs with the help of auxiliary inverters for extra gain. A 0.55 mm2 chip is fabricated in a 0.18 μm CMOS process. Measurements show that the prototype five-path TI BP ΔΣ modulator achieves 50 dB DR and 46 dB SNDR with 10 MHz bandwidth at 50 MHz IF while dissipating only 2 mW.

Original languageEnglish
Article number6913582
Pages (from-to)80-89
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume62
Issue number1
DOIs
Publication statusPublished - 2015 Jan 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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