Abstract
A 2 mW 50 dB-DR 10 MHz-BW bandpass (BP) delta-sigma (ΔΣ) modulator for a digital-IF receiver is presented. It is based on a power-efficient time-interleaved (TI) architecture, which uses a recursive loop and a feed-forward topology. To further improve its power-efficiency, the ADC employs inverter-based OTAs with the help of auxiliary inverters for extra gain. A 0.55 mm2 chip is fabricated in a 0.18 μm CMOS process. Measurements show that the prototype five-path TI BP ΔΣ modulator achieves 50 dB DR and 46 dB SNDR with 10 MHz bandwidth at 50 MHz IF while dissipating only 2 mW.
Original language | English |
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Article number | 6913582 |
Pages (from-to) | 80-89 |
Number of pages | 10 |
Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
Volume | 62 |
Issue number | 1 |
DOIs | |
Publication status | Published - 2015 Jan 1 |
Bibliographical note
Publisher Copyright:© 2004-2012 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering