This paper presents a 20-b read-out IC with ±40-mV full-scale range that is intended for use with bridge transducers. It consists of a current-feedback instrumentation amplifier (CFIA) followed by a switched-capacitor incremental ΔΣ ADC. The CFIA's offset and 1/ f noise are mitigated by chopping, while its gain accuracy and gain drift are improved by applying dynamic element matching to its input and feedback transconductors. Their mismatch is reduced by a digitally assisted correction loop, which further reduces the CFIA's gain drift. Finally, bulk-biasing and impedance-balancing techniques are used to reduce the common-mode dependency of these transconductors, which would otherwise limit the achievable gain accuracy. The combination of these techniques enables the read-out IC to achieve 140-dB CMRR, a worst-case gain error of 0.04% over a 0-2.5 V common-mode range, a maximum gain drift of 0.7 ppm° C and an INL of 5 ppm. After applying nested-chopping, the read-out IC achieves 50-nV offset, 6-nV/° C offset drift, a thermal noise floor of 16.2 nV/√Hz and a 0.1-mHz 1/ f noise corner. Implemented in a 0.7-μm CMOS technology, the prototype read-out IC consumes 270 μA from a 5-V supply.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering