A 20-Gb/s current-mode optical receiver is realized in a 0.13-μm CMOS process, which consists of a common-gate transimpedance amplifier (TIA) with on-chip transformers, a six-stage postamplifier (PA) with an offset cancellation network, and an output buffer. The transformer-based inductive peaking technique is exploited in the TIA to isolate the parasitic capacitances at high-impedance nodes and, hence, to enlarge the bandwidth. The PA incorporates source degeneration and interleaving active feedback techniques to achieve wide bandwidth and flat frequency response so as not to degrade the operation speed of the whole optical receiver. Measured results demonstrate 60-dBΩ transimpedance gain, 12.6-GHz bandwidth even with 0.4-pF large input parasitic capacitance, -13-dBm sensitivity for a 10-12 bit error rate, and 38.3-mW power consumption from a single 1.2-V supply.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2010 May|
Bibliographical noteFunding Information:
Manuscript received October 30, 2009; revised February 9, 2010; accepted March 8, 2010. Date of current version May 14, 2010. This work was supported in part by the Ministry of Education, Science and Technology, Korean Government, under Korea Science and Engineering Foundation Grant 2009063084 and in part by Seoul R&BD Program (NT080509). This paper was recommended by Associate Editor V. Stojanovic.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering