A 200×160-pixel CMOS fingerprint recognition SoC with adaptable column-parallel processors

Seong Jin Kim; Kwang Hyun Lee; Sang Wook Han; Euisik Yoon

A 200×160-pixel CMOS fingerprint recognition SoC with adaptable column-parallel processors

Seong Jin Kim, Kwang Hyun Lee, Sang Wook Han, Euisik Yoon

Yonsei Advanced Science Institute

Research output: Contribution to journal › Conference article › peer-review

Abstract

A CMOS fingerprint recognition SoC with embedded column-parallel processors is optimized for 2D digital image processing. The processor employs self-configuration features for adaptive filter operations and the pixel includes a sensing block, ADC and frame memory without area penalty. The total image processing time is less than 360ms at 10MHz.

Original language	English
Article number	13.7
Pages (from-to)	198-199
Number of pages	2
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	48
Publication status	Published - 2005
Event	2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States Duration: 2005 Feb 6 → 2005 Feb 10

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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title = "A 200×160-pixel CMOS fingerprint recognition SoC with adaptable column-parallel processors",

abstract = "A CMOS fingerprint recognition SoC with embedded column-parallel processors is optimized for 2D digital image processing. The processor employs self-configuration features for adaptive filter operations and the pixel includes a sensing block, ADC and frame memory without area penalty. The total image processing time is less than 360ms at 10MHz.",

author = "Kim, {Seong Jin} and Lee, {Kwang Hyun} and Han, {Sang Wook} and Euisik Yoon",

year = "2005",

language = "English",

volume = "48",

pages = "198--199",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2005 IEEE International Solid-State Circuits Conference, ISSCC ; Conference date: 06-02-2005 Through 10-02-2005",

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AU - Kim, Seong Jin

AU - Lee, Kwang Hyun

AU - Han, Sang Wook

AU - Yoon, Euisik

PY - 2005

Y1 - 2005

N2 - A CMOS fingerprint recognition SoC with embedded column-parallel processors is optimized for 2D digital image processing. The processor employs self-configuration features for adaptive filter operations and the pixel includes a sensing block, ADC and frame memory without area penalty. The total image processing time is less than 360ms at 10MHz.

AB - A CMOS fingerprint recognition SoC with embedded column-parallel processors is optimized for 2D digital image processing. The processor employs self-configuration features for adaptive filter operations and the pixel includes a sensing block, ADC and frame memory without area penalty. The total image processing time is less than 360ms at 10MHz.

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M3 - Conference article

AN - SCOPUS:28144445340

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SP - 198

EP - 199

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

M1 - 13.7

T2 - 2005 IEEE International Solid-State Circuits Conference, ISSCC

Y2 - 6 February 2005 through 10 February 2005

ER -

A 200×160-pixel CMOS fingerprint recognition SoC with adaptable column-parallel processors

Abstract

All Science Journal Classification (ASJC) codes

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