A 200×160-pixel CMOS fingerprint recognition SoC with adaptable column-parallel processors

Seong Jin Kim, Kwang Hyun Lee, Sang Wook Han, Euisik Yoon

Research output: Contribution to journalConference article


A CMOS fingerprint recognition SoC with embedded column-parallel processors is optimized for 2D digital image processing. The processor employs self-configuration features for adaptive filter operations and the pixel includes a sensing block, ADC and frame memory without area penalty. The total image processing time is less than 360ms at 10MHz.

Original languageEnglish
Article number13.7
Pages (from-to)198-199
Number of pages2
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication statusPublished - 2005 Dec 6
Event2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: 2005 Feb 62005 Feb 10


All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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