A 2.1 M pixels, 120 frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture

Youngcheol Chae, Jimin Cheon, Seunghyun Lim, Minho Kwon, Kwisung Yoo, Wunki Jung, Dong Hun Lee, Seogheon Ham, Gunhee Han

Research output: Contribution to journalArticle

129 Citations (Scopus)


This paper presents a 2.1 M pixel, 120 frame/s CMOS image sensor with column-parallel delta-sigma (Δ Σ) ADC architecture. The use of a second-order Δ Σ ADC improves the conversion speed while reducing the random noise (RN) level as well. The Δ Σ ADC employing an inverter-based Δ Σ modulator and a compact decimation filter is accommodated within a fine pixel pitch of 2.25-μm and improves energy efficiency while providing a high frame-rate of 120 frame/s. A prototype image sensor has been fabricated with a 0.13- μm CMOS process. Measurement results show a RN of 2.4 erms- and a dynamic range of 73 dB. The power consumption of the prototype image sensor is only 180 mW. This work achieves the energy efficiency of 1.7 e-nJ.

Original languageEnglish
Article number5641589
Pages (from-to)236-247
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Issue number1
Publication statusPublished - 2011 Jan 1


All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this