A 2.1 mW 2 MHz-BW 73.8 dB-SNDR Buffer-Embedded Noise-Shaping SAR ADC

Taewoong Kim, Youngcheol Chae

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)


This paper presents a buffer-embedded noise-shaping SAR ADC, whose input buffer separates the capacitive DAC (CDAC) and the sampling capacitor (CS) at the input and output of the input buffer. This compensates for the non-linearity of the input buffer and reduces the CS value, resulting in a significant power saving in the input buffer. This buffer-embedded architecture enables the effective implementation of the following passive loop filter and enhances energy efficiency. A bootstrapping switch in the feedback CDAC is coupled to the output of the buffer, thereby avoiding a signal dependency due to the parasitic capacitance of the switch. The buffer-embedded noise-shaping SAR ADC occupies 0.08mm2 in a 65 nm CMOS process and features a parasitic input capacitor of 0.2 pF. It achieves 73.8 dB SNDR, 77 dB DR and 87.3 dB SFDR in a 2 MHz bandwidth without any calibration. Including the power consumption of the input buffer, the ADC consumes only 2.1 mW.

Original languageEnglish
Pages (from-to)5029-5037
Number of pages9
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number12
Publication statusPublished - 2021 Dec 1

Bibliographical note

Publisher Copyright:
© 2004-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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