A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture

Youngcheol Chae, Jimin Cheon, Seunghyun Lim, Dongmyung Lee, Minho Kwon, Kwisung Yoo, Wunki Jung, Dong Hun Lee, Seogheon Ham, Gunhee Han

Research output: Chapter in Book/Report/Conference proceedingConference contribution

38 Citations (Scopus)

Abstract

Over the last few years, the demands for high-density and high-speed imaging have increased drastically. Since CMOS image sensors have the advantages of low power consumption and easy system integration, they have become dominant over CCDs in the consumer market [1-4]. A column-parallel ADC architecture is the most widely used ADC in CMOS image sensors for high-speed and low-power operation [2-6]. The column-parallel architecture can be classified as: successive-approximation register (SAR) [2], cyclic [3], single-slope (SS) [4], and delta-sigma (ΔΣ) [5,6] ADCs. Although SAR ADCs have been utilized for high-speed imaging, such as UDTV, they require a DAC in a column, whose area is unacceptably large for consumer electronics with a fine pixel pitch. Cyclic ADCs have also been reported in high-speed imaging, but they have high power consumption and high noise levels. Since SS ADCs provide relatively high resolution with minimum area, they have been widely used in CMOS image sensors. However, SS ADCs require very fast clock signals leading to high power consumption in the case of high-speed imaging. Although ΔΣ ADCs have been investigated for low-noise imaging, they have only been applied for low-speed imaging with large pixel pitch because of the complexity of ΔΣ modulators and following decimation filters.

Original languageEnglish
Title of host publication2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers
Pages394-395
Number of pages2
DOIs
Publication statusPublished - 2010 May 18
Event2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - San Francisco, CA, United States
Duration: 2010 Feb 72010 Feb 11

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume53
ISSN (Print)0193-6530

Other

Other2010 IEEE International Solid-State Circuits Conference, ISSCC 2010
CountryUnited States
CitySan Francisco, CA
Period10/2/710/2/11

Fingerprint

Parallel architectures
Image sensors
Imaging techniques
Electric power utilization
Pixels
Consumer electronics
Charge coupled devices
Modulators
Clocks

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Chae, Y., Cheon, J., Lim, S., Lee, D., Kwon, M., Yoo, K., ... Han, G. (2010). A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture. In 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers (pp. 394-395). [5433974] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 53). https://doi.org/10.1109/ISSCC.2010.5433974
Chae, Youngcheol ; Cheon, Jimin ; Lim, Seunghyun ; Lee, Dongmyung ; Kwon, Minho ; Yoo, Kwisung ; Jung, Wunki ; Lee, Dong Hun ; Ham, Seogheon ; Han, Gunhee. / A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture. 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers. 2010. pp. 394-395 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).
@inproceedings{383cee832e074a519415ab920570f659,
title = "A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture",
abstract = "Over the last few years, the demands for high-density and high-speed imaging have increased drastically. Since CMOS image sensors have the advantages of low power consumption and easy system integration, they have become dominant over CCDs in the consumer market [1-4]. A column-parallel ADC architecture is the most widely used ADC in CMOS image sensors for high-speed and low-power operation [2-6]. The column-parallel architecture can be classified as: successive-approximation register (SAR) [2], cyclic [3], single-slope (SS) [4], and delta-sigma (ΔΣ) [5,6] ADCs. Although SAR ADCs have been utilized for high-speed imaging, such as UDTV, they require a DAC in a column, whose area is unacceptably large for consumer electronics with a fine pixel pitch. Cyclic ADCs have also been reported in high-speed imaging, but they have high power consumption and high noise levels. Since SS ADCs provide relatively high resolution with minimum area, they have been widely used in CMOS image sensors. However, SS ADCs require very fast clock signals leading to high power consumption in the case of high-speed imaging. Although ΔΣ ADCs have been investigated for low-noise imaging, they have only been applied for low-speed imaging with large pixel pitch because of the complexity of ΔΣ modulators and following decimation filters.",
author = "Youngcheol Chae and Jimin Cheon and Seunghyun Lim and Dongmyung Lee and Minho Kwon and Kwisung Yoo and Wunki Jung and Lee, {Dong Hun} and Seogheon Ham and Gunhee Han",
year = "2010",
month = "5",
day = "18",
doi = "10.1109/ISSCC.2010.5433974",
language = "English",
isbn = "9781424460342",
series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",
pages = "394--395",
booktitle = "2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers",

}

Chae, Y, Cheon, J, Lim, S, Lee, D, Kwon, M, Yoo, K, Jung, W, Lee, DH, Ham, S & Han, G 2010, A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture. in 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers., 5433974, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 53, pp. 394-395, 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010, San Francisco, CA, United States, 10/2/7. https://doi.org/10.1109/ISSCC.2010.5433974

A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture. / Chae, Youngcheol; Cheon, Jimin; Lim, Seunghyun; Lee, Dongmyung; Kwon, Minho; Yoo, Kwisung; Jung, Wunki; Lee, Dong Hun; Ham, Seogheon; Han, Gunhee.

2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers. 2010. p. 394-395 5433974 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 53).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture

AU - Chae, Youngcheol

AU - Cheon, Jimin

AU - Lim, Seunghyun

AU - Lee, Dongmyung

AU - Kwon, Minho

AU - Yoo, Kwisung

AU - Jung, Wunki

AU - Lee, Dong Hun

AU - Ham, Seogheon

AU - Han, Gunhee

PY - 2010/5/18

Y1 - 2010/5/18

N2 - Over the last few years, the demands for high-density and high-speed imaging have increased drastically. Since CMOS image sensors have the advantages of low power consumption and easy system integration, they have become dominant over CCDs in the consumer market [1-4]. A column-parallel ADC architecture is the most widely used ADC in CMOS image sensors for high-speed and low-power operation [2-6]. The column-parallel architecture can be classified as: successive-approximation register (SAR) [2], cyclic [3], single-slope (SS) [4], and delta-sigma (ΔΣ) [5,6] ADCs. Although SAR ADCs have been utilized for high-speed imaging, such as UDTV, they require a DAC in a column, whose area is unacceptably large for consumer electronics with a fine pixel pitch. Cyclic ADCs have also been reported in high-speed imaging, but they have high power consumption and high noise levels. Since SS ADCs provide relatively high resolution with minimum area, they have been widely used in CMOS image sensors. However, SS ADCs require very fast clock signals leading to high power consumption in the case of high-speed imaging. Although ΔΣ ADCs have been investigated for low-noise imaging, they have only been applied for low-speed imaging with large pixel pitch because of the complexity of ΔΣ modulators and following decimation filters.

AB - Over the last few years, the demands for high-density and high-speed imaging have increased drastically. Since CMOS image sensors have the advantages of low power consumption and easy system integration, they have become dominant over CCDs in the consumer market [1-4]. A column-parallel ADC architecture is the most widely used ADC in CMOS image sensors for high-speed and low-power operation [2-6]. The column-parallel architecture can be classified as: successive-approximation register (SAR) [2], cyclic [3], single-slope (SS) [4], and delta-sigma (ΔΣ) [5,6] ADCs. Although SAR ADCs have been utilized for high-speed imaging, such as UDTV, they require a DAC in a column, whose area is unacceptably large for consumer electronics with a fine pixel pitch. Cyclic ADCs have also been reported in high-speed imaging, but they have high power consumption and high noise levels. Since SS ADCs provide relatively high resolution with minimum area, they have been widely used in CMOS image sensors. However, SS ADCs require very fast clock signals leading to high power consumption in the case of high-speed imaging. Although ΔΣ ADCs have been investigated for low-noise imaging, they have only been applied for low-speed imaging with large pixel pitch because of the complexity of ΔΣ modulators and following decimation filters.

UR - http://www.scopus.com/inward/record.url?scp=77952114328&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77952114328&partnerID=8YFLogxK

U2 - 10.1109/ISSCC.2010.5433974

DO - 10.1109/ISSCC.2010.5433974

M3 - Conference contribution

AN - SCOPUS:77952114328

SN - 9781424460342

T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SP - 394

EP - 395

BT - 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers

ER -

Chae Y, Cheon J, Lim S, Lee D, Kwon M, Yoo K et al. A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture. In 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers. 2010. p. 394-395. 5433974. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2010.5433974